Datasheet

XMEGA A4U [DATASHEET]
Atmel-8387G-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_03/2014
90
Table 36-31. SPI timing characteristics and requirements.
36.1.16 Two-Wire Interface Characteristics
Table 36-32 on page 91 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7 on page 90.
Figure 36-7. Two-wire interface bus timing.
Symbol Parameter Condition Min. Typ. Max. Units
t
SCK
SCK period Master
(See Table 21-4 in
XMEGA AU Manual)
ns
t
SCKW
SCK high/low width Master 0.5*SCK
t
SCKR
SCK rise time Master 2.7
t
SCKF
SCK fall time Master 2.7
t
MIS
MISO setup to SCK Master 10
t
MIH
MISO hold after SCK Master 10
t
MOS
MOSI setup SCK Master 0.5*SCK
t
MOH
MOSI hold after SCK Master 1
t
SSCK
Slave SCK Period Slave 4*t Clk
PER
t
SSCKW
SCK high/low width Slave 2*t Clk
PER
t
SSCKR
SCK rise time Slave 1600
t
SSCKF
SCK fall time Slave 1600
t
SIS
MOSI setup to SCK Slave 3
t
SIH
MOSI hold after SCK Slave t Clk
PER
t
SSS
SS setup to SCK Slave 21
t
SSH
SS hold after SCK Slave 20
t
SOS
MISO setup SCK Slave 8
t
SOH
MISO hold after SCK Slave 13
t
SOSS
MISO setup after SS low Slave 11
t
SOSH
MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO