Datasheet

123
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
Problem fix/Workaround
None.
26. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
27. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
36.2.3 rev. A
Not sampled.