Datasheet

6
XMEGA A1U [DATASHEET]
Atmel-8385H-AVR-ATxmega64A1U-128A1U-Datasheet–AVR–04/2014
3.1 Block Diagram
Figure 3-1. XMEGA A1U Block Diagram.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
EVENT ROUTING NETWORK
DMA
Controller
SRAM
EBI
ADCA
DACA
ACA
DACB
ADCB
ACB
OCD
Int. Refs.
PORT K (8)
PORT J (8)
PORT H (8)
PDI
PH[0..7]
PJ[0..7]
PK[0..7]
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
DES
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7] PE[0..7] PF[0..7]
PORT D (8)
TCD0:1
USARTD0:1
TWID
SPID
TCF0:1
USARTF0:1
TWIF
SPIF
TCE0:1
USARTE0:1
TWIE
SPIE
PORT E (8) PORT F (8)
Tempref
VCC/10
AES
USB
PORT R (2)
XTAL1
XTAL2
PR[0..1]
TOSC1
TOSC2
PQ[0..3]
PORT Q (4)
DATA BUS
NVM Controller
MORPEEhsalF
IRCOM
BUS Matrix
CPU
PORT E/F
Digital function
Analog function
Bus masters, programming, debug, test
Oscillator/Crystal/Clock
General Purpose I/O
EBI