Datasheet

15
XMEGA A1U [DATASHEET]
Atmel-8385H-AVR-ATxmega64A1U-128A1U-Datasheet–AVR–04/2014
7.10 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External
memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the
external bus interface. Refer to the instruction summary for more details on instructions and instruction timing.
7.11 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
7.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.14 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 15 shows the Flash Program Memory organization. Flash write and erase operations are performed
on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used
for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address
bits (FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Table 7-3 on page 16 shows EEPROM memory organization for the Atmel AVR XMEGA A1U devices. EEPROM write
and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at
a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in
the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Devices PC size Flash Page Size FWORD FPAGE Application Boot
bits bytes words Size No of pages Size No of pages
ATxmega64A1U 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A1U 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16