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Atmel-8385H-AVR-ATxmega64A1U-128A1U-Datasheet–AVR–04/2014

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 64K - 128KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 2KBytes EEPROM

 4K - 8KBytes internal SRAM

 External bus interface for up to 16Mbytes SRAM

 External bus interface for up to 128Mbit SDRAM

 Peripheral features

 Four-channel DMA controller

 Eight-channel event system

 Eight 16-bit timer/counters

 Four timer/counters with 4 output compare or input capture channels

 Four timer/counters with 2 output compare or input capture channels

 High resolution extension on all timer/counters

 Advanced waveform extension (AWeX) on two timer/counters

 One USB device interface

 USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant

 32 Endpoints with full configuration flexibility

 Eight USARTs with IrDA support for one USART

 Four two-wire interfaces with dual address match (I

C and SMBus compatible)

 Four serial peripheral interfaces (SPIs)

 AES and DES crypto engine

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE

802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 Two sixteen channel, 12-bit, 2msps Analog to Digital Converters

 Two Two-channel, 12-bit, 1msps Digital to Analog Converters

 Four Analog Comparators (ACs) with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interfaces

 JTAG (IEEE 1149.1 compliant) interface, including boundary scan

 PDI (Program and Debug Interface)

 I/O and packages

 78 Programmable I/O pins

 100 lead TQFP

 100 ball BGA

 100 ball VFBGA

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA A1U Microcontroller

ATxmega128A1U; ATxmega64A1U

Summary of content (214 pages)

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8/16-bit Atmel XMEGA A1U Microcontroller ATxmega128A1U; ATxmega64A1U Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories  64K - 128KBytes of in-system self-programmable flash  4K - 8KBytes boot section  2KBytes EEPROM  4K - 8KBytes internal SRAM  External bus interface for up to 16Mbytes SRAM  External bus interface for up to 128Mbit SDRAM  Peripheral features  Four-channel DMA controller  Eight-channel event system  Eight 16-
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1.
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2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout.
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Figure 2-2. BGA-pinout. Top view 1 2 3 4 5 6 Bottom view 7 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 2-1. BGA-pinout.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block Diagram Figure 3-1. XMEGA A1U Block Diagram. Digital function Bus masters, programming, debug, test Analog function EBI Oscillator/Crystal/Clock PR[0..1] XTAL1 PQ[0..3] TOSC1 General Purpose I/O XTAL2 TOSC2 PORT R (2) PORT Q (4) Real Time Counter Watchdog Oscillator DATA BUS DACA PA[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  Atmel AVR XMEGA AU manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU manual describes the modules and peripherals in depth.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   142 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. 7. Memories 7.
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The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a flash memory signature rows for calibration data, device identification, serial number etc. 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device.
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7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
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Figure 7-2. Data memory map (hexadecimal address). Byte Address ATxmega64A1U 0 Byte Address 0 I/O Registers (4K) FFF I/O Registers (4KB) FFF 1000 1000 EEPROM (2K) 17FF EEPROM (2K) 17FF RESERVED 2000 RESERVED 2000 Internal SRAM (4K) 2FFF Internal SRAM (8K) 3FFF 4000 3000 External Memory (0 to 16MB) FFFFFF 7.6 ATxmega128A1U External Memory (0 to 16MB) FFFFFF EEPROM XMEGA AU devices have EEPROM for nonvolatile data storage.
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7.10 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the external bus interface.
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Table 7-3. Number of Bytes and Pages in the EEPROM.
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8. DMAC – Direct Memory Access Controller 8.
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9. Event System 9.
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10. System Clock and Clock options 10.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators:  32MHz run-time calibrated and tunable oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output   External clock options  0.4MHz - 16MHz crystal oscillator 32.
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Figure 10-1. The clock system, clock sources, and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 USB clkUSB Brown-out Detector System Clock Prescalers Watchdog Timer Prescaler clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 10.3 0.
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency.
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11. Power Management and Sleep Modes 11.1 Features  Power management for adjusting power consumption and functions  Five sleep modes  Idle Power down  Power save  Standby  Extended standby   Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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11.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 11.3.
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12. System Control and Reset 12.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 12.
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12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin.
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13. WDT – Watchdog Timer 13.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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14. Interrupts and Programmable Multilevel Interrupt Controller 14.
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Program address (base address) Source Interrupt description 0x028 TCC1_INT_base Timer/counter 1 on port C interrupt base 0x030 SPIC_INT_vect SPI on port C interrupt vector 0x032 USARTC0_INT_base USART 0 on port C interrupt base 0x038 USARTC1_INT_base USART 1 on port C interrupt base 0x03E AES_INT_vect AES interrupt vector 0x040 NVM_INT_base Nonvolatile memory interrupt base 0x044 PORTB_INT_base Port B interrupt base 0x048 ACB_INT_base Analog comparator on port B interrupt base 0x0
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Program address (base address) Source Interrupt description 0x0E4 TCF1_INT_base Timer/counter 1 on port F interrupt base 0x0EC SPIF_INT_vector SPI ion port F interrupt base 0x0EE USARTF0_INT_base USART 0 on port F interrupt base 0x0F4 USARTF1_INT_base USART 1 on port F interrupt base 0x0FA USB_INT_base USB on port D interrupt base XMEGA A1U [DATASHEET] Atmel-8385H-AVR-ATxmega64A1U-128A1U-Datasheet–AVR–04/2014 29
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15. I/O Ports 15.
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15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).
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15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
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15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 33. Figure 15-7. Input sensing system overview Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.
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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 16.
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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins.
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17. TC2 – Time/Counter Type 2 17.
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18. AWeX – Advanced Waveform Extension 18.
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19. Hi-Res – High Resolution Extension 19.1 Features  Increases waveform generator resolution up to 8x (three bits)  Supports frequency, single-slope PWM and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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20. RTC – 16-bit Real-Time Counter 20.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator   Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 20.
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21. USB – Universal Serial Bus Interface 21.1 Features  One USB 2.0 full speed (12Mbps) and low speed (1.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB.
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22. TWI – Two-Wire Interface 22.
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PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and TWIF. 23. SPI – Serial Peripheral Interface 23.1 Features  Four identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 23.
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24. USART 24.
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25. IRCOM – IR Communication Module 25.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2Kbps  Selectable pulse modulation scheme  3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled   Built-in filtering  Can be connected to and used by any USART 25.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
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26. AES and DES Crypto Engine 26.1 Features  Data Encryption Standard (DES) CPU instruction  Advanced Encryption Standard (AES) crypto module  DES Instruction  Encryption and decryption DES supported  Encryption/decryption in 16 CPU clock cycles per 8-byte block   AES crypto module  Encryption and decryption Supports 128-bit keys  Supports XOR data load mode to the state memory  Encryption/decryption in 375 clock cycles per 16-byte block  26.
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27. CRC – Cyclic Redundancy Check Generator 27.
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28. EBI – External Bus Interface 28.
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29. ADC – 12-bit Analog to Digital Converter 29.1 Features  Two Analog to Digital Converters  12-bit resolution  Up to two million samples per second  Two inputs can be sampled simultaneously using ADC and 1x gain stage Four inputs can be sampled within 1.5µs  Down to 2.5µs conversion time with 8-bit resolution  Down to 3.
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Figure 29-1. ADC overview. ADC0 Compare • •• ADC15 ADC0 Internal signals VINP CH0 Result •• • ADC7 ADC4 CH1 Result Threshold (Int Req) ½x - 64x CH2 Result • •• ADC7 Int. signals < > Internal signals CH3 Result VINN ADC0 • •• ADC3 Int. signals Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting.
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30. DAC – 12-bit Digital to Analog Converter 30.
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A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC. The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both.
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31. AC – Analog Comparator 31.
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Figure 31-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis DAC Voltage Scaler Enable ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 31-2. Figure 31-2. Analog comparator window function.
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32. PDI – Programming and Debugging 32.
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33. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 33.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 33.1.
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33.1.5 Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 33.1.
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33.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the the first table where this apply. Table 33-1.
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Table 33-3. Port C - alternate functions. PORT C PIN# INTERRUPT TCC0(1)(2) AWEXC TCC1 USARTC0(3) GND 13 VCC 14 PC0 15 SYNC OC0A OC0ALS PC1 16 SYNC OC0B OC0AHS XCK0 PC2 17 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 18 SYNC OC0D OC0BHS TXD0 PC4 19 SYNC OC0CLS OC1A PC5 20 SYNC OC0CHS OC1B PC6 21 SYNC PC7 22 SYNC Notes: 1. 2. 3. 4. 5. 6.
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PORT E PIN # INTERRUPT TCE0 AWEXE TCE1 PE3 38 SYNC OC0D OC0BHS PE4 39 SYNC OC0CLS OC1A PE5 40 SYNC OC0CHS OC1B PE6 41 SYNC PE7 42 SYNC USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT clkPER EVOUT TXD0 SS XCK1 MOSI OC0DLS RXD1 MISO OC0DHS TXD1 SCK Table 33-6. Port F - alternate functions.
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Table 33-8. Port J - alternate functions.
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Table 33-11. Port R - alternate functions.
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34. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1U. For complete register description and summary for each peripheral module, refer to the XMEGA AU manual. Table 34-1. Peripheral module address map.
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Base address Name Description 0x0440 EBI External Bus Interface 0x0480 TWIC Two Wire Interface on port C 0x0490 TWID Two Wire Interface on port D 0x04A0 TWIE Two Wire Interface on port E 0x04B0 TWIF Two Wire Interface on port F 0x04C0 USB USB Device 0x0600 PORTA Port A 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x06E0 PORTH Port H 0x0700 PORTJ Port J 0x0720 PORTK Port K 0x07C0 PORTQ Port Q 0x07E0 POR
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Base address Name Description 0x0A80 AWEXE Advanced Waveform Extension on port E 0x0A90 HIRESE High Resolution Extension on port E 0x0AA0 USARTE0 USART 0 on port E 0x0AB0 USARTE1 USART 1 on port E 0x0AC0 SPIE Serial Peripheral Interface on port E 0x0B00 TCF0 Timer/Counter 0 on port F 0x0B40 TCF1 Timer/Counter 1 on port F 0x0B90 HIRESF 0x0BA0 USARTF0 USART 0 on port F 0x0BB0 USARTF1 USART 1 on port F 0x0BC0 SPIF High Resolution Extension on port F Serial Peripheral Interfac
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35.
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Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3 (1) call Subroutine PC  k None 3 / 4 (1) RET Subroutine Return PC  STACK None 4 / 5 (1) RETI Interrupt Return PC  STACK I 4 / 5 (1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with
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Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd  (k) None 2 (1)(2) LD Rd, X Load Indirect Rd  (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y+1 None 1 (1)(2) LD Rd, -Y Load In
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Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1 (1) Pop Register from Stack Rd  STACK None 2 (1) Z, Rd Exchange RAM location Temp Rd (Z)    Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z)    Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp R
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Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr.
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36. Packaging information 36.1 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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36.2 100C1 0.12 Z E Marked A1 Identifier SIDE VIEW D A TOP VIEW A1 Øb e A1 Corner 0.90 TYP 10 9 8 7 6 5 4 3 2 1 A 0.90 TYP B C D COMMON DIMENSIONS (Unit of Measure = mm) E D1 F e SYMBOL MIN H A 1.10 – 1.20 I A1 0.30 0.35 0.40 D 8.90 9.00 9.10 G J E1 BOTTOM VIEW NOM MAX E 8.90 9.00 9.10 D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e NOTE 0.80 TYP 5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 100C1, 100-ball, 9 x 9 x 1.
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36.3 100C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 E1 SIDE VIEW 100 - Ø0.35 ± 0.05 K J H G e COMMON DIMENSIONS (Unit of Measure = mm) F D1 E SYMBOL MIN NOM MAX D A – – 1.00 C A1 0.20 – – B A2 0.65 – – D 6.90 7.00 7.10 A D1 1 2 3 4 5 6 7 8 9 5.85 BSC 10 E A1 BALL CORNER b e BOTTOM VIEW NOTE 6.90 7.00 E1 7.10 5.85 BSC b 0.30 0.35 e 0.40 0.65 BSC 07/11/2012 Package Drawing Contact: packagedrawings@atmel.
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37. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. Note: 37.1 For devices that are not available yet, preliminary values in this datasheet are based on simulations, and/or characterization of similar AVR XMEGA microcontrollers.
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Table 37-3. Operating voltage and frequency. Symbol Parameter ClkCPU Condition CPU clock frequency Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 37-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 37-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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37.1.3 Current consumption Table 37-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk ICC T = 25°C Min. T = 85°C 50 VCC = 3.0V 95 VCC = 1.8V 350 VCC = 3.0V 700 VCC = 1.8V 650 700 1.2 1.4 15 20 VCC = 3.0V Power-save power consumption(2) Reset power consumption Notes: 1.
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Table 37-5. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 1.0 32.768kHz int. oscillator 27 Max. Units 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 120 310 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference Watchdog timer 560 µA 1.0 Continuous mode 126 Sampled mode, includes ULP oscillator 1.2 BOD Internal 1.0V reference 89 Temperature sensor 83 3.
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37.1.4 Wake-up time from sleep modes Table 37-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 10 32MHz internal oscillator 5.5 Max.
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37.1.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 37-7. I/O pin characteristics. Symbol Parameter Condition Min. Typ. Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.7*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3*VCC VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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37.1.6 ADC characteristics Table 37-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 5.0 k Cin Input capacitance Switched 5.
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Table 37-10. Accuracy characteristics. Symbol Parameter RES Resolution INL(1) DNL(1) Integral non-linearity Differential non-linearity Offset Error Condition(2) Programmable to 12-bit 1. 2. Max. Units 11 11.5 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 2000ksps, differential mode VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 single ended mode ±1.5 ±4 guaranteed monotonic <±0.5 <±1 lsb -1 mV Temperature drift <0.
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Symbol Parameter Gain Error Offset Error, input referred Condition Min. 1x gain, normal mode -0.7 8x gain, normal mode -3.0 64x gain, normal mode -4.8 1x gain, normal mode 0.4 8x gain, normal mode 0.4 64x gain, normal mode 0.4 1x gain, normal mode Noise 8x gain, normal mode 1. Max. Units % mV 0.6 VCC = 3.6V mV rms 2.0 Ext. VREF 64x gain, normal mode Note: Typ.
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Table 37-14. Accuracy characteristics. Symbol RES Parameter Condition Min. Input resolution VREF= Ext 1.0V INL(1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL(1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3.0 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
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Symbol Parameter Condition VCC = 3.0V, T= 85°C tdelay Propagation delay Min. mode = HS mode = HS VCC = 3.0V, T= 85°C Typ. Max. 60 90 60 mode = LP Units ns 130 Current source calibration range Single mode 2 8 Double mode 4 16 64-Level Voltage Scaler Integral non-linearity (INL) µs 0.3 0.5 lsb 37.1.9 Bandgap and Internal 1.0V Reference Characteristics Table 37-16. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Condition Min.
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37.1.11 External Reset Characteristics Table 37-18. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 86 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.60*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.40*VCC V 37.1.12 Power-on Reset Characteristics Table 37-19. Power-on reset characteristics.
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Table 37-21. Programming time. Symbol Parameter Chip Erase Flash EEPROM Notes: 1. 2. Condition Min. Typ. (1) 64KB Flash, EEPROM(2) and SRAM Erase 55 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Max. Units ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 37.1.14 Clock and Oscillator Characteristics 37.1.14.1 Calibrated 32.
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37.1.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 37-24. 32MHz internal oscillator characteristics. Symbol Parameter Tunable frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Max. Units 35 MHz Factory calibrated frequency Factory calibration accuracy Typ. 32 T = 85C, VCC= 3.0V -1.5 1.5 % DFLL calibration step size 0.24 37.1.14.4 32kHz Internal ULP Oscillator characteristics Table 37-25.
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37.1.14.6 External clock characteristics Figure 37-3. External clock drive waveform. tCH tCH tCF tCR VIH1 VIL1 tCL tCK Table 37-27. External clock(1). Symbol Parameter Clock frequency(2) 1/tCK tCK Clock period tCH/CL Clock high/low time VIL/IH Low/high level input voltage tCK Reduction in period from one clock cycle to the next Notes: 1. 2. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 90 VCC = 2.7 - 3.6V 142 Units MHz VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.
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37.1.14.7 External 16MHz crystal oscillator and XOSC characteristics Table 37-28. External 16MHz crystal oscillator and XOSC characteristics. . Symbol Parameter Condition Min. Typ. FRQRANGE=0 <10 FRQRANGE=1, 2, 3 <1 Max. Cycle to cycle jitter Units ns FRQRANGE=0 <0.5 FRQRANGE=1 <0.05 FRQRANGE=2 <0.005 FRQRANGE=3 <0.
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Symbol Parameter Condition Start-up time Min. Typ. XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0 XOSCPWR=0, FRQRANGE=1 2MHz crystal, CL=20pF 2.6 XOSCPWR=0, FRQRANGE=2 8MHz crystal, CL=20pF 0.8 XOSCPWR=0, FRQRANGE=3 12MHz crystal, CL=20pF 1.0 XOSCPWR=1, FRQRANGE=3 16MHz crystal, CL=20pF 1.4 CXTAL1 Parasitic capacitance XTAL1 pin 6 CXTAL2 Parasitic capacitance XTAL2 pin 10 CLOAD Parasitic capacitance load 3.8 Note: 1. Max.
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The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 37.1.15 SPI Characteristics Figure 37-5. SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 37-6. SPI timing requirements in slave mode.
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Table 37-30. SPI timing characteristics and requirements. Symbol Parameter tSCK SCK period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.
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37.1.16 EBI characteristics Table 37-31. EBI SRAM characteristics and requirements. Symbol Parameter tClkPER2 SRAM clock period Condition Min. Typ. Max. Units 0.
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Table 37-32. EBI SDRAM characteristics and requirements. Symbol Parameter Condition tClkPER2 SDRAM clock period Min. Typ. Max. Units 0.5*tClkPER tAH SDRAM address hold time 0.5*tClkPER2 tAS SDRAM address setup time 0.5*tClkPER2 tCH SDRAM clock high-level width 0.5*tClkPER2 tCL SDRAM clock low-level width 0.5*tClkPER2 tCKH SDRAM CKE hold time 0.5*tClkPER2 tCKS SDRAM CKE setup time 0.5*tClkPER2 tCMH SDRAM CS, RAS, CAS, WE, DQM hold time 0.
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Table 37-33. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. Units VIH Input high voltage 0.7*VCC VCC+0.5 VIL Input low voltage -0.5 0.3*VCC Vhys Hysteresis of Schmitt trigger inputs 0.05*VCC (1) 0 0 0.4 20+0.1Cb (1)(2) 0 20+0.
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37.2 ATxmega128A1U 37.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 37-34 on page 96 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 37-34. Absolute maximum ratings.
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Figure 37-8. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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37.2.3 Current consumption Table 37-37. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk ICC T = 25°C Min. T = 85°C 50 VCC = 3.0V 95 VCC = 1.8V 350 VCC = 3.0V 700 VCC = 1.8V 650 700 1.2 1.4 15 20 VCC = 3.0V Power-save power consumption(2) Reset power consumption Notes: 1.
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Table 37-38. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 1.0 32.768kHz int. oscillator 27 Max. Units 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 120 310 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference Watchdog timer 560 µA 1.0 Continuous mode 126 Sampled mode, includes ULP oscillator 1.2 BOD Internal 1.0V reference 89 Temperature sensor 83 3.
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37.2.4 Wake-up time from sleep modes Table 37-39. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ.(1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 10 32MHz internal oscillator 5.5 Max.
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37.2.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 37-40. I/O pin characteristics. Symbol Parameter Condition Min. Typ. Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.7*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3*VCC VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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37.2.6 ADC characteristics Table 37-41. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 5.0 k Cin Input capacitance Switched 5.
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Table 37-43. Accuracy characteristics. Symbol Parameter RES Resolution INL(1) DNL(1) Integral non-linearity Differential non-linearity Offset Error Condition(2) Programmable to 12-bit 1. 2. Max. Units 11 11.5 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 2000ksps, differential mode VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 single ended mode ±1.5 ±4 guaranteed monotonic <±0.5 <±1 lsb -1 mV Temperature drift <0.
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Symbol Parameter Gain Error Offset Error, input referred Condition Min. 1x gain, normal mode -0.7 8x gain, normal mode -3.0 64x gain, normal mode -4.8 1x gain, normal mode 0.4 8x gain, normal mode 0.4 64x gain, normal mode 0.4 1x gain, normal mode Noise 8x gain, normal mode 1. Max. Units % mV 0.6 VCC = 3.6V mV rms 2.0 Ext. VREF 64x gain, normal mode Note: Typ.
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Table 37-47. Accuracy characteristics. Symbol RES Parameter Condition Min. Input resolution VREF= Ext 1.0V INL(1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL(1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3.0 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
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Symbol Parameter Condition VCC = 3.0V, T= 85°C tdelay Propagation delay Min. mode = HS mode = HS VCC = 3.0V, T= 85°C Typ. Max. 60 90 60 mode = LP Units ns 130 Current source calibration range Single mode 2 8 Double mode 4 16 64-Level Voltage Scaler Integral non-linearity (INL) µs 0.3 0.5 lsb 37.2.9 Bandgap and Internal 1.0V Reference Characteristics Table 37-49. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Condition Min.
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37.2.11 External Reset Characteristics Table 37-51. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 86 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.60*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.40*VCC V 37.2.12 Power-on Reset Characteristics Table 37-52. Power-on reset characteristics.
PAGE 108
Table 37-54. Programming time. Symbol Parameter Chip Erase Flash EEPROM Notes: 1. 2. Condition Min. Typ. (1) 128KB Flash, EEPROM(2) and SRAM Erase 75 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Max. Units ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 37.2.14 Clock and Oscillator Characteristics 37.2.14.1 Calibrated 32.
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37.2.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 37-57. 32MHz internal oscillator characteristics. Symbol Parameter Tunable frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Max. Units 35 MHz Factory calibrated frequency Factory calibration accuracy Typ. 32 T = 85C, VCC= 3.0V -1.5 1.5 % DFLL calibration step size 0.24 37.2.14.4 32kHz Internal ULP Oscillator characteristics Table 37-58.
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37.2.14.6 External clock characteristics Figure 37-10.External clock drive waveform. tCH tCH tCF tCR VIH1 VIL1 tCL tCK Table 37-60. External clock(1). Symbol Parameter Clock frequency(2) 1/tCK tCK Clock period tCH/CL Clock high/low time VIL/IH Low/high level input voltage tCK Reduction in period from one clock cycle to the next Notes: 1. 2. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 90 VCC = 2.7 - 3.6V 142 Units MHz VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.
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37.2.14.7 External 16MHz crystal oscillator and XOSC characteristics Table 37-61. External 16MHz crystal oscillator and XOSC characteristics. . Symbol Parameter Condition Min. Typ. FRQRANGE=0 <10 FRQRANGE=1, 2, 3 <1 Max. Cycle to cycle jitter Units ns FRQRANGE=0 <0.5 FRQRANGE=1 <0.05 FRQRANGE=2 <0.005 FRQRANGE=3 <0.
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Symbol Parameter Condition Start-up time Min. Typ. XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0 XOSCPWR=0, FRQRANGE=1 2MHz crystal, CL=20pF 2.6 XOSCPWR=0, FRQRANGE=2 8MHz crystal, CL=20pF 0.8 XOSCPWR=0, FRQRANGE=3 12MHz crystal, CL=20pF 1.0 XOSCPWR=1, FRQRANGE=3 16MHz crystal, CL=20pF 1.4 CXTAL1 Parasitic capacitance XTAL1 pin 6 CXTAL2 Parasitic capacitance XTAL2 pin 10 CLOAD Parasitic capacitance load 3.8 Note: 1. Max.
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The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 37.2.15 SPI Characteristics Figure 37-12.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 37-13.SPI timing requirements in slave mode.
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Table 37-63. SPI timing characteristics and requirements. Symbol Parameter tSCK SCK period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.
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37.2.16 EBI characteristics Table 37-64. EBI SRAM characteristics and requirements. Symbol Parameter tClkPER2 SRAM clock period Condition Min. Typ. Max. Units 0.
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Table 37-65. EBI SDRAM characteristics and requirements. Symbol Parameter Condition tClkPER2 SDRAM clock period Min. Typ. Max. Units 0.5*tClkPER tAH SDRAM address hold time 0.5*tClkPER2 tAS SDRAM address setup time 0.5*tClkPER2 tCH SDRAM clock high-level width 0.5*tClkPER2 tCL SDRAM clock low-level width 0.5*tClkPER2 tCKH SDRAM CKE hold time 0.5*tClkPER2 tCKS SDRAM CKE setup time 0.5*tClkPER2 tCMH SDRAM CS, RAS, CAS, WE, DQM hold time 0.
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Table 37-66. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. Units VIH Input high voltage 0.7*VCC VCC+0.5 VIL Input low voltage -0.5 0.3*VCC Vhys Hysteresis of Schmitt trigger inputs 0.05*VCC (1) 0 0 0.4 20+0.1Cb (1)(2) 0 20+0.
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38. Typical Characteristics 38.1 ATxmega64A1U 38.1.1 Current consumption 38.1.1.1 Active mode supply current Figure 38-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 38-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 18 3.3 V 16 3.0 V 14 2.7 V ICC [mA] 12 10 2.2 V 8 6 4 1.
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Figure 38-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 175 -40°C 160 25°C 85°C 105°C 145 I CC [µA] 130 115 100 85 70 55 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 900 -40°C 25°C 85°C 105°C 830 760 I CC [µA] 690 620 550 480 410 340 270 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1800 -40 °C 25 °C 85 °C 105 °C 1650 1500 I CC [µA] 1350 1200 1050 900 750 600 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 7.5 -40 °C 25 °C 85 °C 105 °C 6.9 6.3 I CC [mA] 5.7 5.1 4.5 3.9 3.3 2.7 2.1 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 21 -40 °C 20 25°C 85°C 105°C 19 I CC [mA] 18 17 16 15 14 13 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 38.1.1.2 Idle mode supply current Figure 38-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 250 225 3.3 V 200 3.0 V 175 2.7 V 150 2.2 V 125 1.8 V 100 75 50 25 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 38-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 8 3.3 V 7 3.0 V ICC [mA] 6 2.7 V 5 4 2.2 V 3 2 1.8 V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 38-10.Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 41.5 40.0 105°C 38.5 I CC [µA] 37.0 85 °C -40°C 35.5 25°C 34.0 32.5 31.0 29.5 28.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-11.Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 270 105 °C 85 °C 25°C -40°C 250 230 I CC [µA] 210 190 170 150 130 110 90 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-12.Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 600 -40°C 25°C 85°C 105°C 550 I CC [µA] 500 450 400 350 300 250 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-13.Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 3100 -40°C 25°C 85°C 105°C 2800 I CC [µA] 2500 2200 1900 1600 1300 1000 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-14.Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 8650 -40°C 25°C 85°C 105°C 8300 7950 I CC [µA] 7600 7250 6900 6550 6200 5850 5500 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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38.1.1.3 Power-down mode supply current Figure 38-15.Power-down mode supply current vs. Temperature. All functions disabled. 6.00 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 5.25 4.50 I CC [µA] 3.75 3.00 2.25 1.50 0.75 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-16.Power-down mode supply current vs. Temperature. Sampled BOD with Watchdog Timer running on ULP oscillator. 6.05 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 5.30 I CC [µA] 4.55 3.80 3.05 2.30 1.55 0.
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38.1.1.4 Power-save mode supply current Figure 38-17.Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.1.1.5 Standby mode supply current Figure 38-18. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.5 105°C 11.5 10.5 ICC [µA] 9.5 85°C 8.5 25°C -40°C 7.5 6.5 5.5 4.5 3.5 2.
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Figure 38-19. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.1.2 I/O Pin Characteristics 38.1.2.1 Pull-up Figure 38-20. I/O pin pull-up resistor current vs. pin voltage. VCC = 1.8V. 80 70 I pin [µA] 60 50 40 30 -40°C 25°C 85°C 105°C 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 38-21. I/O pin pull-up resistor current vs. pin voltage. VCC = 3.0V. 120 105 90 I pin [µA] 75 60 45 30 -40°C 25 °C 85 °C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 38-22. I/O pin pull-up resistor current vs. pin voltage. VCC = 3.3V. 140 120 I pin [µA] 100 80 60 40 -40°C 25 °C 85 °C 105°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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38.1.2.2 Output Voltage vs. Sink/Source Current Figure 38-23.I/O pin output voltage vs. source current. VCC = 1.8V. 1.85 1.70 1.55 V PIN [V] 1.40 1.25 1.10 0.95 -40°C 0.80 25°C 85°C 105°C 0.65 0.50 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -12 -9 -6 -3 0 IPIN [mA] Figure 38-24.I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.9 2.6 V PIN [V] 2.3 2.0 1.7 1.4 -40°C 1.1 105°C 25°C 0.8 85°C 0.
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Figure 38-25.I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.2 2.9 2.6 VPIN [V] 2.3 2.0 -40°C 1.7 25°C 1.4 1.1 85°C 0.8 105°C 0.5 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 38-26.I/O pin output voltage vs. source current. 3.8 3.6V 3.4 3.3V VPIN [V] 3.0 2.7V 2.6 2.2 1.8V 1.8 1.4 1.
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Figure 38-27.I/O pin output voltage vs. sink current. VCC = 1.8V. 1.6 105°C 1.4 1.2 85°C VPIN [V] 1.0 0.8 25°C -40°C 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 38-28.I/O pin output voltage vs. sink current. VCC = 3.0V. 1.20 1.05 105°C 85°C 0.90 25°C -40°C V PIN [V] 0.75 0.60 0.45 0.30 0.15 0.
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Figure 38-29.I/O pin output voltage vs. sink current. VCC = 3.3V. 1.08 105°C 85°C 25°C -40°C 0.96 0.84 V PIN [V] 0.72 0.60 0.48 0.36 0.24 0.12 0.00 0 4 8 12 16 20 24 28 32 IPIN [mA] Figure 38-30.I/O pin output voltage vs. sink current. 1.50 1.8V 1.35 1.20 VPIN [V] 1.05 0.90 2.7V 3.3V 3.6V 0.75 0.60 0.45 0.30 0.15 0.
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38.1.2.3 Thresholds and Hysteresis Figure 38-31.I/O pin input threshold voltage vs. VCC. T = 25°C. 1.85 VIH 1.70 VIL Vthreshold [V] 1.55 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-32.I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.88 -40°C 25°C 85°C 105°C 1.76 Vthreshold[V] 1.64 1.52 1.4 1.28 1.16 1.04 0.92 0.8 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.
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Figure 38-33.I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.70 105°C 85 °C 25 °C -40°C 1.55 V threshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.6 VCC [V] Figure 38-34.I/O pin input hysteresis vs. VCC. 0.36 -40 °C 0.33 Vthreshold [V] 0.3 0.27 25°C 0.24 0.21 85°C 0.18 0.15 105°C 0.12 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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38.1.3 ADC Characteristics Figure 38-35.INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.5 Single-ended unsigned mode INL [LSB] 1.4 1.3 Differential mode 1.2 1.1 1 Single-ended signed mode 0.9 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 1850 2000 VREF [V] Figure 38-36.INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 2.0V external. 1.17 1.14 Differential mode 1.11 Single-ended Unsigned mode INL [LSB] 1.08 1.05 1.02 Single-ended Signed mode 0.
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Figure 38-37.INL error vs. input code 2 1.5 INL [LSB] 1 0.5 0 -0.5 -1 -1.5 -2 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 38-38.DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.3 1.2 Single-ended unsigned mode 1.1 DNL [LSB] 1 0.9 0.8 0.7 0.6 Differential mode 0.5 0.4 Single-ended signed mode 0.3 0.2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-39.DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 2.0V external. 0.53 0.51 Differential mode DNL [LSB] 0.49 0.47 Single-ended signed mode 0.45 0.43 0.41 0.39 Single-ended unsigned mode 0.37 0.35 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sample rate [ksps] Figure 38-40.DNL error vs. input code. 0.7 0.6 DNL [LSB] 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.
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Figure 38-41.Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 10 9 Single-ended signed mode Gain Error [mV] 8 7 6 5 Single-ended unsigned mode 4 3 2 Differential mode 1 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-42.Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 9 8 Single-ended signed mode Gain error [mV] 7 6 5 4 Single-ended unsigned mode 3 2 Differential mode 1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.
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Figure 38-43.ADC Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -0.8 -0.85 Offset [mV] -0.9 -0.95 -1 -1.05 Differential mode -1.1 -1.15 -1.2 -1.25 -1.3 -1.35 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-44.Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V.
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Figure 38-45.ADC Offset vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.2 -0.25 Offset [mV] -0.3 -0.35 Differential mode -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-46.Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.47 0.46 Differential Noise [mV RMS] 0.45 0.44 0.43 0.42 0.41 0.4 0.39 0.38 0.37 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-47.Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.42 Noise [mV RMS] 0.41 Differential 0.4 0.39 0.38 0.37 0.36 0.35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 38.1.4 DAC Characteristics Figure 38-48.DAC INL error vs. VREF. VCC = 3.6V, external reference, room temperature. 1.9 1.8 INL [LSB] 1.7 1.6 1.5 1.4 1.3 1.2 1.1 25°C 1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-49.DAC DNL error vs. VREF. VCC = 3.6V, external reference, room temperature. 1.35 1.25 DNL [LSB] 1.15 1.05 0.95 0.85 0.75 0.65 25°C 0.55 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-50.DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . TBD 0.183 0.181 Noise [mV RMS] 0.179 0.177 0.175 0.173 0.171 0.169 0.167 0.
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38.1.5 Analog Comparator Characteristics Figure 38-51.Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 53 105° C 85 °C 25 °C -40°C 51 49 V HYST [mV] 47 45 43 41 39 37 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-52.Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 37.0 35.5 105°C 85 °C 34.0 VHYST [mV] 32.5 31.0 25 °C 29.5 -40°C 28.0 26.5 25.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-53.Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 53 105° C 85 °C 25 °C -40°C 51 49 V HYST [mV] 47 45 43 41 39 37 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-54.Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 77 105°C 85°C 74 71 VHYST [mV] 68 65 25°C 62 59 -40°C 56 53 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-55.Analog comparator current source vs. calibration value. Temperature = 25C. 8 7 I [µA] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 38-56.Analog comparator current source vs. calibration value. VCC = 3.0V. 6.0 5.7 I CURRENTSOURCE [µA] 5.4 5.1 4.8 4.5 4.2 3.9 -40°C 25 °C 85°C 105°C 3.6 3.3 3.0 0 2 4 6 8 10 12 14 16 CALIB[3..
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Figure 38-57.Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.30 0.25 INL [LSB] 0.20 0.15 0.10 0.05 25°C 0.00 -0.05 -0.10 0 7 14 21 28 35 42 49 56 63 SCALEFAC 38.1.6 Internal 1.0V reference Characteristics Figure 38-58. ADC/DAC Internal 1.0V reference vs. temperature. 3.6 V 3.3 V 3.0 V 2.7 V 1.8 V 1.6 V 1.005 1.002 0.999 Bandgap Voltage [V] 0.996 0.993 0.990 0.987 0.984 0.981 0.978 0.
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38.1.7 BOD Characteristics Figure 38-59.BOD thresholds vs. temperature. BOD level = 1.6V. 1.650 Rising Vcc 1.645 1.640 Falling Vcc 1.635 V BOT [V] 1.630 1.625 1.620 1.615 1.610 1.605 1.600 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-60.BOD thresholds vs. temperature. BOD level = 3.0V. 3.090 Rising Vcc 3.075 3.060 V BOT [V] 3.045 Falling Vcc 3.030 3.015 3.000 2.985 2.970 2.
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38.1.8 External Reset Characteristics Figure 38-61.Minimum Reset pin pulse width vs. VCC. 124 116 108 t RST [ns] 100 105°C 92 25°C -40°C 84 76 68 85°C 60 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-62.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 I RESET [µA] 60 50 40 30 20 -40°C 10 85°C 105°C 25°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 38-63.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 105 I RESET [µA] 90 75 60 45 -40°C 30 25°C 15 85°C 105°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 38-64.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 160 140 120 I RESET [µA] 100 80 60 40 -40°C 25°C 20 85°C 105°C 0 0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45 2.80 3.15 3.
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Figure 38-65.Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. V threshold [V] 2.20 -40°C 2.05 25°C 1.90 85°C 105°C 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-66.Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.70 -40°C 25°C 1.55 85°C 105°C V threshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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38.1.9 Power-on Reset Characteristics Figure 38-67.Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 1500 -40°C 1350 25°C 85°C 105 °C 1200 ICC [µA] 1050 900 750 600 450 300 150 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VCC [V] Figure 38-68.Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 1350 -40°C 1200 25°C 85°C 105 °C 1050 ICC [µA] 900 750 600 450 300 150 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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38.1.10 Oscillator Characteristics 38.1.10.1 Ultra Low-Power internal oscillator Figure 38-69.Ultra Low-Power internal oscillator frequency vs. temperature. 30.0 29.6 Frequency [kHz] 29.2 28.8 28.4 28.0 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 27.6 27.2 26.8 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] 38.1.10.2 32.768kHz Internal Oscillator Figure 38-70. 32.768kHz internal oscillator frequency vs. temperature. 32.900 1.8 V 2.2 V 2.7 V 3.3 V 3.0 V 32.850 Frequency [kHz] 32.800 32.750 32.
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Figure 38-71. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 47 Frequency [kHz] 44 41 38 35 32 29 26 23 20 0 30 60 90 120 150 180 210 240 270 RC32KCAL[7..0] 38.1.10.3 2MHz Internal Oscillator Figure 38-72. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.07 2.06 Frequency [MHz] 2.05 2.04 2.03 2.02 2.01 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 2.00 1.99 1.
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Figure 38-73. 2MHz internal oscillator frequency vs. temperature. DFLL enabled. 2.0100 1.8 V 2.2 V 2.7 V 2.0075 Frequency [MHz] 2.0050 3.3 V 3.0 V 2.0025 2.0000 1.9975 1.9950 1.9925 1.9900 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-74. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.24 Frequency step size [%] 0.23 0.21 0.20 0.18 0.17 105 °C -40 °C 85 °C 25 °C 0.15 0.14 0.
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38.1.10.4 32MHz Internal Oscillator Figure 38-75. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 34.2 33.9 Frequency [MHz] 33.6 33.3 33.0 32.7 32.4 32.1 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 31.8 31.5 31.2 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-76. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 32.05 3.3 V Frequency [MHz] 32.00 1.8 V 2.2 V 31.95 3.0 V 31.90 2.7 V 31.85 31.80 31.
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Figure 38-77. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.30 Frequency Step size [%] 0.28 0.26 0.24 0.22 0.20 85°C 0.18 105°C 25°C -40°C 0.16 0.14 0.12 0.10 0 15 30 45 60 75 90 105 120 135 CALA Figure 38-78. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V, DFLL disabled.
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38.1.10.5 32MHz internal oscillator calibrated to 48MHz Figure 38-79. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 51.50 51.00 Frequency [MHz] 50.50 50.00 49.50 49.00 48.50 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 48.00 47.50 47.00 46.50 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-80. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.16 1.8 V 2.2 V 2.7 V 3.0 V 3.3 V 48.08 Frequency [MHz] 48.00 47.
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Figure 38-81. 32MHz internal oscillator CALA calibration step size. Using 48MHz calibration value from signature row, VCC = 3.0V. 0.30 Frequency Step size [%] 0.28 0.26 0.24 0.22 0.20 105°C 85°C 25°C -40°C 0.18 0.16 0.14 0.12 0.10 0 15 30 45 60 75 90 105 120 135 CALA 38.1.11 PDI characteristics Figure 38-82. Maximum PDI frequency vs. VCC. 34 -40°C 25 °C 85 °C 105°C 31 28 f MAX [MHz] 25 22 19 16 13 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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38.2 ATxmega128A1U 38.2.1 Current consumption 38.2.1.1 Active mode supply current Figure 38-83. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 38-84. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 18 3.3 V 16 3.0 V 14 2.7 V ICC [mA] 12 10 2.2 V 8 6 4 1.
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Figure 38-85. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 175 -40°C 160 25°C 85°C 105°C 145 I CC [µA] 130 115 100 85 70 55 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-86. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 900 -40°C 25°C 85°C 105°C 830 760 I CC [µA] 690 620 550 480 410 340 270 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-87. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1800 -40 °C 25 °C 85 °C 105 °C 1650 1500 I CC [µA] 1350 1200 1050 900 750 600 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-88. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 7.5 -40 °C 25 °C 85 °C 105 °C 6.9 6.3 I CC [mA] 5.7 5.1 4.5 3.9 3.3 2.7 2.1 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-89. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 21 -40 °C 20 25°C 85°C 105°C 19 I CC [mA] 18 17 16 15 14 13 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 38.2.1.2 Idle mode supply current Figure 38-90.Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 250 225 3.3 V 200 3.0 V 175 2.7 V 150 2.2 V 125 1.8 V 100 75 50 25 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 38-91.Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 8 3.3 V 7 3.0 V ICC [mA] 6 2.7 V 5 4 2.2 V 3 2 1.8 V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 38-92.Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 41.5 40.0 105°C 38.5 I CC [µA] 37.0 85 °C -40°C 35.5 25°C 34.0 32.5 31.0 29.5 28.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-93.Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 270 105 °C 85 °C 25°C -40°C 250 230 I CC [µA] 210 190 170 150 130 110 90 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-94.Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 600 -40°C 25°C 85°C 105°C 550 I CC [µA] 500 450 400 350 300 250 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-95.Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 3100 -40°C 25°C 85°C 105°C 2800 I CC [µA] 2500 2200 1900 1600 1300 1000 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-96.Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 8650 -40°C 25°C 85°C 105°C 8300 7950 I CC [µA] 7600 7250 6900 6550 6200 5850 5500 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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38.2.1.3 Power-down mode supply current Figure 38-97.Power-down mode supply current vs. Temperature. All functions disabled. 6.00 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 5.25 4.50 I CC [µA] 3.75 3.00 2.25 1.50 0.75 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-98.Power-down mode supply current vs. Temperature. Sampled BOD with Watchdog Timer running on ULP oscillator. 6.05 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 5.30 I CC [µA] 4.55 3.80 3.05 2.30 1.55 0.
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38.2.1.4 Power-save mode supply current Figure 38-99.Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.2.1.5 Standby mode supply current Figure 38-100. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.5 105°C 11.5 10.5 ICC [µA] 9.5 85°C 8.5 25°C -40°C 7.5 6.5 5.5 4.5 3.5 2.
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Figure 38-101. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.2.2 I/O Pin Characteristics 38.2.2.1 Pull-up Figure 38-102. I/O pin pull-up resistor current vs. pin voltage. VCC = 1.8V. 80 70 I pin [µA] 60 50 40 30 -40°C 25°C 85°C 105°C 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 38-103. I/O pin pull-up resistor current vs. pin voltage. VCC = 3.0V. 120 105 90 I pin [µA] 75 60 45 30 -40°C 25 °C 85 °C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 38-104. I/O pin pull-up resistor current vs. pin voltage. VCC = 3.3V. 140 120 I pin [µA] 100 80 60 40 -40°C 25 °C 85 °C 105°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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38.2.2.2 Output Voltage vs. Sink/Source Current Figure 38-105.I/O pin output voltage vs. source current. VCC = 1.8V. 1.85 1.70 1.55 V PIN [V] 1.40 1.25 1.10 0.95 -40°C 0.80 25°C 85°C 105°C 0.65 0.50 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -12 -9 -6 -3 0 IPIN [mA] Figure 38-106.I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.9 2.6 V PIN [V] 2.3 2.0 1.7 1.4 -40°C 1.1 105°C 25°C 0.8 85°C 0.
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Figure 38-107.I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.2 2.9 2.6 VPIN [V] 2.3 2.0 -40°C 1.7 25°C 1.4 1.1 85°C 0.8 105°C 0.5 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 38-108.I/O pin output voltage vs. source current. 3.8 3.6V 3.4 3.3V VPIN [V] 3.0 2.7V 2.6 2.2 1.8V 1.8 1.4 1.
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Figure 38-109.I/O pin output voltage vs. sink current. VCC = 1.8V. 1.6 105°C 1.4 1.2 85°C VPIN [V] 1.0 0.8 25°C -40°C 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 38-110.I/O pin output voltage vs. sink current. VCC = 3.0V. 1.20 1.05 105°C 85°C 0.90 25°C -40°C V PIN [V] 0.75 0.60 0.45 0.30 0.15 0.
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Figure 38-111.I/O pin output voltage vs. sink current. VCC = 3.3V. 1.08 105°C 85°C 25°C -40°C 0.96 0.84 V PIN [V] 0.72 0.60 0.48 0.36 0.24 0.12 0.00 0 4 8 12 16 20 24 28 32 IPIN [mA] Figure 38-112.I/O pin output voltage vs. sink current. 1.50 1.8V 1.35 1.20 VPIN [V] 1.05 0.90 2.7V 3.3V 3.6V 0.75 0.60 0.45 0.30 0.15 0.
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38.2.2.3 Thresholds and Hysteresis Figure 38-113.I/O pin input threshold voltage vs. VCC. T = 25°C. 1.85 VIH 1.70 VIL Vthreshold [V] 1.55 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-114.I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.88 -40°C 25°C 85°C 105°C 1.76 Vthreshold[V] 1.64 1.52 1.4 1.28 1.16 1.04 0.92 0.8 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.
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Figure 38-115.I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.70 105°C 85 °C 25 °C -40°C 1.55 V threshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.6 VCC [V] Figure 38-116.I/O pin input hysteresis vs. VCC. 0.36 -40 °C 0.33 Vthreshold [V] 0.3 0.27 25°C 0.24 0.21 85°C 0.18 0.15 105°C 0.12 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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38.2.3 ADC Characteristics Figure 38-117.INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.5 Single-ended unsigned mode INL [LSB] 1.4 1.3 Differential mode 1.2 1.1 1 Single-ended signed mode 0.9 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 1850 2000 VREF [V] Figure 38-118.INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 2.0V external. 1.17 1.14 Differential mode 1.11 Single-ended Unsigned mode INL [LSB] 1.08 1.05 1.
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Figure 38-119.INL error vs. input code 2 1.5 INL [LSB] 1 0.5 0 -0.5 -1 -1.5 -2 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 38-120.DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.3 1.2 Single-ended unsigned mode 1.1 DNL [LSB] 1 0.9 0.8 0.7 0.6 Differential mode 0.5 0.4 Single-ended signed mode 0.3 0.2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-121.DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 2.0V external. 0.53 0.51 Differential mode DNL [LSB] 0.49 0.47 Single-ended signed mode 0.45 0.43 0.41 0.39 Single-ended unsigned mode 0.37 0.35 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sample rate [ksps] Figure 38-122.DNL error vs. input code. 0.7 0.6 DNL [LSB] 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.
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Figure 38-123.Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 10 9 Single-ended signed mode Gain Error [mV] 8 7 6 5 Single-ended unsigned mode 4 3 2 Differential mode 1 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-124.Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 9 8 Single-ended signed mode Gain error [mV] 7 6 5 4 Single-ended unsigned mode 3 2 Differential mode 1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.
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Figure 38-125.ADC Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -0.8 -0.85 Offset [mV] -0.9 -0.95 -1 -1.05 Differential mode -1.1 -1.15 -1.2 -1.25 -1.3 -1.35 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-126.Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V.
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Figure 38-127.ADC Offset vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.2 -0.25 Offset [mV] -0.3 -0.35 Differential mode -0.4 -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-128.Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.47 0.46 Differential Noise [mV RMS] 0.45 0.44 0.43 0.42 0.41 0.4 0.39 0.38 0.37 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-129.Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.42 Noise [mV RMS] 0.41 Differential 0.4 0.39 0.38 0.37 0.36 0.35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 38.2.4 DAC Characteristics Figure 38-130.DAC INL error vs. VREF. VCC = 3.6V, external reference, room temperature. 1.9 1.8 INL [LSB] 1.7 1.6 1.5 1.4 1.3 1.2 1.1 25°C 1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 38-131.DAC DNL error vs. VREF. VCC = 3.6V, external reference, room temperature. 1.35 1.25 DNL [LSB] 1.15 1.05 0.95 0.85 0.75 0.65 25°C 0.55 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 38-132.DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . TBD 0.183 0.181 Noise [mV RMS] 0.179 0.177 0.175 0.173 0.171 0.169 0.167 0.
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38.2.5 Analog Comparator Characteristics Figure 38-133.Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 53 105° C 85 °C 25 °C -40°C 51 49 V HYST [mV] 47 45 43 41 39 37 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-134.Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 37.0 35.5 105°C 85 °C 34.0 VHYST [mV] 32.5 31.0 25 °C 29.5 -40°C 28.0 26.5 25.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-135.Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 53 105° C 85 °C 25 °C -40°C 51 49 V HYST [mV] 47 45 43 41 39 37 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-136.Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 77 105°C 85°C 74 71 VHYST [mV] 68 65 25°C 62 59 -40°C 56 53 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 38-137.Analog comparator current source vs. calibration value. Temperature = 25C. 8 7 I [µA] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 38-138.Analog comparator current source vs. calibration value. VCC = 3.0V. 6.0 5.7 I CURRENTSOURCE [µA] 5.4 5.1 4.8 4.5 4.2 3.9 -40°C 25 °C 85°C 105°C 3.6 3.3 3.0 0 2 4 6 8 10 12 14 16 CALIB[3..
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Figure 38-139.Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.30 0.25 INL [LSB] 0.20 0.15 0.10 0.05 25°C 0.00 -0.05 -0.10 0 7 14 21 28 35 42 49 56 63 SCALEFAC 38.2.6 Internal 1.0V reference Characteristics Figure 38-140. ADC/DAC Internal 1.0V reference vs. temperature. 3.6 V 3.3 V 3.0 V 2.7 V 1.8 V 1.6 V 1.005 1.002 0.999 Bandgap Voltage [V] 0.996 0.993 0.990 0.987 0.984 0.981 0.978 0.
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38.2.7 BOD Characteristics Figure 38-141.BOD thresholds vs. temperature. BOD level = 1.6V. 1.650 Rising Vcc 1.645 1.640 Falling Vcc 1.635 V BOT [V] 1.630 1.625 1.620 1.615 1.610 1.605 1.600 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-142.BOD thresholds vs. temperature. BOD level = 3.0V. 3.090 Rising Vcc 3.075 3.060 V BOT [V] 3.045 Falling Vcc 3.030 3.015 3.000 2.985 2.970 2.
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38.2.8 External Reset Characteristics Figure 38-143.Minimum Reset pin pulse width vs. VCC. 124 116 108 t RST [ns] 100 105°C 92 25°C -40°C 84 76 68 85°C 60 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-144.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 I RESET [µA] 60 50 40 30 20 -40°C 10 85°C 105°C 25°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 38-145.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 105 I RESET [µA] 90 75 60 45 -40°C 30 25°C 15 85°C 105°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 38-146.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 160 140 120 I RESET [µA] 100 80 60 40 -40°C 25°C 20 85°C 105°C 0 0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45 2.80 3.15 3.
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Figure 38-147.Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. V threshold [V] 2.20 -40°C 2.05 25°C 1.90 85°C 105°C 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 38-148.Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.70 -40°C 25°C 1.55 85°C 105°C V threshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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38.2.9 Power-on Reset Characteristics Figure 38-149.Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 1500 -40°C 1350 25°C 85°C 105 °C 1200 ICC [µA] 1050 900 750 600 450 300 150 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VCC [V] Figure 38-150.Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 1350 -40°C 1200 25°C 85°C 105 °C 1050 ICC [µA] 900 750 600 450 300 150 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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38.2.10 Oscillator Characteristics 38.2.10.1 Ultra Low-Power internal oscillator Figure 38-151.Ultra Low-Power internal oscillator frequency vs. temperature. 30.0 29.6 Frequency [kHz] 29.2 28.8 28.4 28.0 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 27.6 27.2 26.8 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] 38.2.10.2 32.768kHz Internal Oscillator Figure 38-152. 32.768kHz internal oscillator frequency vs. temperature. 32.900 1.8 V 2.2 V 2.7 V 3.3 V 3.0 V 32.850 Frequency [kHz] 32.800 32.750 32.
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Figure 38-153. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 47 Frequency [kHz] 44 41 38 35 32 29 26 23 20 0 30 60 90 120 150 180 210 240 270 RC32KCAL[7..0] 38.2.10.3 2MHz Internal Oscillator Figure 38-154. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.07 2.06 Frequency [MHz] 2.05 2.04 2.03 2.02 2.01 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 2.00 1.99 1.
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Figure 38-155. 2MHz internal oscillator frequency vs. temperature. DFLL enabled. 2.0100 1.8 V 2.2 V 2.7 V 2.0075 Frequency [MHz] 2.0050 3.3 V 3.0 V 2.0025 2.0000 1.9975 1.9950 1.9925 1.9900 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-156. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.24 Frequency step size [%] 0.23 0.21 0.20 0.18 0.17 105 °C -40 °C 85 °C 25 °C 0.15 0.14 0.
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38.2.10.4 32MHz Internal Oscillator Figure 38-157. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 34.2 33.9 Frequency [MHz] 33.6 33.3 33.0 32.7 32.4 32.1 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 31.8 31.5 31.2 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-158. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 32.05 3.3 V Frequency [MHz] 32.00 1.8 V 2.2 V 31.95 3.0 V 31.90 2.7 V 31.85 31.80 31.
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Figure 38-159. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.30 Frequency Step size [%] 0.28 0.26 0.24 0.22 0.20 85°C 0.18 105°C 25°C -40°C 0.16 0.14 0.12 0.10 0 15 30 45 60 75 90 105 120 135 CALA Figure 38-160. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V, DFLL disabled.
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38.2.10.5 32MHz internal oscillator calibrated to 48MHz Figure 38-161. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 51.50 51.00 Frequency [MHz] 50.50 50.00 49.50 49.00 48.50 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 48.00 47.50 47.00 46.50 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 38-162. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.16 1.8 V 2.2 V 2.7 V 3.0 V 3.3 V 48.08 Frequency [MHz] 48.
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Figure 38-163. 32MHz internal oscillator CALA calibration step size. Using 48MHz calibration value from signature row, VCC = 3.0V. 0.30 Frequency Step size [%] 0.28 0.26 0.24 0.22 0.20 105°C 85°C 25°C -40°C 0.18 0.16 0.14 0.12 0.10 0 15 30 45 60 75 90 105 120 135 CALA 38.2.11 PDI characteristics Figure 38-164. Maximum PDI frequency vs. VCC. 34 -40°C 25 °C 85 °C 105°C 31 28 f MAX [MHz] 25 22 19 16 13 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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39. Errata 39.1 ATxmega64A1U 39.1.1 Rev.
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4. Configuration of PGM and CWCM is not as described in XMEGA AU Manual Configuration of common waveform channel mode (CWCM) and pattern generation mode (PGM), is not as described in the XMEGA AU manual. Problem fix/Workaround Configure PWM and CWCM according to the Table 39-1 on page 201. Table 39-1. PWM and CWCM configuration. PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 5.
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8. USB, when receiving 1023Byte length isochronous frame, it will corrupt 1024th SRAM location When USB is configured for isochronous operation and 1023Byte data payload size, the 1024th RAM location that is directly after the endpoint RAM buffer will be corrupted. Problem fix/Workaround Allocate 1024bytes RAM buffer when using 1023 isochronous endpoint. This workaround is implemented in all USB software and source code delivered from Atmel in the AVR Software Framework. 9.
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Problem fix/Workaround Use the ADC in single ended signed mode. 15. ADC has increased linearity error when using the gain stage above 500ksps The INL error for gain stage is increased to above 20LSB for sampling speed exceeding 500 ksps. Problem fix/Workaround None. 16. DAC Offset calibration range too small when using AVCC as reference If using AVCC as reference, the DAC offset calibration will not totally remove the offset error. Offset could be up to 100LSB after calibration.
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39.2 ATxmega128A1U 39.2.1 Rev.
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Problem fix/Workaround Configure PWM and CWCM according to the Table 39-1 on page 201. Table 39-2. PWM and CWCM configuration. PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 5. AWEX PWM output after fault restarted with wrong values When recovering from fault state, the PWM output will drive wrong values to the port for up to two CLKPER + one CLKPER4 cycles. Problem fix/Workaround The following seqence can be used in Latched Mode: a. b.
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Problem fix/Workaround Allocate 1024bytes RAM buffer when using 1023 isochronous endpoint. This workaround is implemented in all USB software and source code delivered from Atmel in the AVR Software Framework. 9. USB endpoint table is 16-byte alignment The USB endpoint table uses 16-byte alignment, instead of 16-bit alignment. Problem fix/Workaround Align the endpoint configuration table pointer in SRAM to a 16-byte.
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15. ADC has increased linearity error when using the gain stage above 500ksps The INL error for gain stage is increased to above 20LSB for sampling speed exceeding 500 ksps. Problem fix/Workaround None. 16. DAC Offset calibration range too small when using AVCC as reference If using AVCC as reference, the DAC offset calibration will not totally remove the offset error. Offset could be up to 100LSB after calibration. Problem fix/Workaround Offset adjustment must be partly handled in software. 17.
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40. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 40.1 40.2 8385H – 04/2014 1. Updated “Ordering Information” on page 2. The ATxmega64A1U and ATxmega128A1U @ 105C added. 2. Updated the typical characteristics at 105C in “ATxmega64A1U” on page 118 and “ATxmega128A1U” on page 159. 8385G – 11/2013 1. 40.3 8385F – 12/2012 1. 40.4 40.
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40.7 40.8 8385B – 03/2012 1. Added “Electrical Characteristics” on page 74. 2. Added “Typical Characteristics” on page 118. 3. Updated “Errata” on page 200. 4. Used Atmel new datasheet template that includes Atmel new addresses on the last page. 8385A – 11/2011 1. Initial revision.
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 22 11.1 11.2 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sleep Modes . . . . . . . . . . . . . . . . . . . . . .
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22.1 22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Overview . . . . . . . . . . . . . . . .
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36.3 100C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 37. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 37.1 37.2 ATxmega64A1U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ATxmega128A1U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 38. Typical Characteristics . . . . . . . . . . . . . .
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