Datasheet
18
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
9. DMAC - Direct Memory Access Controller
9.1 Features
Allows High-speed data transfer
From memory to peripheral
From memory to memory
From peripheral to memory
From peripheral to peripheral
4 Channels
From 1 byte and up to 16M bytes transfers in a single transaction
Multiple addressing modes for source and destination address
Increment
Decrement
Static
1, 2, 4, or 8 byte Burst Transfers
Programmable priority between channels
9.2 Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.