Datasheet

15
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
Figure 8-2. Data Memory Map (Hexadecimal address)
8.6 EEPROM
XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space
(default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access.
Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this,
EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal
address 0x1000.
8.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which is used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F,
single- cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A1U is shown in the “Peripheral Module Address
Map” on page 62.
8.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
8.8 External Memory
Four ports can be used for external memory, supporting external SRAM, SDRAM, and memory mapped peripherals such
as LCD displays. Refer to “EBI – External Bus Interface” on page 47. The external memory address space will always
start at the end of internal SRAM.
8.9 Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
Byte Address ATxmega128A1 Byte Address ATxmega64A1
0
I/O Registers
(4 KB)
0
I/O Registers
(4 KB)
FFF FFF
1000
EEPROM
(2 KB)
1000
EEPROM
(2 KB)
17FF 17FF
RESERVED RESERVED
2000
Internal SRAM
(8 KB)
2000
Internal SRAM
(4 KB)
3FFF 2FFF
4000
External Memory
(0 to 16 MB)
3000
External Memory
(0 to 16 MB)
FFFFFF FFFFFF