Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VFBGA 100 (7x7) 8/16-Bit 32 MHz I/O number 78

Not recommended for new designs - Use XMEGA A1U series

8067O–AVR–06/2013

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 64K - 128KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 2 KBBytes EEPROM

 4 KB - 8 KBBytes internal SRAM

 External bus interface for up to 16Mbytes SRAM

 External bus interface for up to 128Mbit SDRAM

 Peripheral features

 Four-channel DMA controller

 Eight-channel event system

 Eight 16-bit timer/counters

 Four timer/counters with 4 output compare or input capture channels

 Four timer/counters with 2 output compare or input capture channels

 High resolution extension on all timer/counters

 Advanced waveform extension (AWeX) on two timer/counters

 Eight USARTs with IrDA support for one USART

 Four two-wire interfaces with dual address match (I

C and SMBus compatible)

 Four serial peripheral interfaces (SPIs)

 AES and DES crypto engine

 16-bit real time counter (RTC) with separate oscillator

 Two sixteen channel, 12-bit, 2msps Analog to Digital Converters

 Two two-channel, 12-bit, 1msps Digital to Analog Converters

 Four Analog Comparators (ACs) with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interfaces

 JTAG (IEEE 1149.1 compliant) interface, including boundary scan

 PDI (Program and Debug Interface)

 I/O and packages

 78 Programmable I/O pins

 100 lead TQFP

 100 ball BGA

 100 ball VFBGA

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit XMEGA A1 Microcontroller

ATxmega128A1 / ATxmega64A1

Preliminary

8067O–AVR–06/2013

Not recommended for new designs -

Use XMEGA A1U series

Summary of content (122 pages)

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8/16-bit XMEGA A1 Microcontroller ATxmega128A1 / ATxmega64A1 Not recommended for new designs - Preliminary Use XMEGA A1U series Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories  64K - 128KBytes of in-system self-programmable flash  4K - 8KBytes boot section  2 KBBytes EEPROM  4 KB - 8 KBBytes internal SRAM  External bus interface for up to 16Mbytes SRAM  External bus interface for up to 128Mbit SDRAM  Peripheral features 
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‘ 1. Ordering Information Ordering Code Flash (B) E2 SRAM 128K + 8K 2 KB 8 KB Speed (MHz) Power Supply Package(1)(2)(3) Temp ATxmega128A1-AU ATxmega128A1-AUR 100A ATxmega64A1-AU 64K + 4K 2 KB 4 KB 128K + 8K 2 KB 8 KB ATxmega64A1-AUR ATxmega128A1-CU ATxmega128A1CUR 32 1.6 - 3.6V 100C1 -40C - 85C ATxmega64A1-CU 64K + 4K 2 KB 4 KB 128K + 8K 2 KB 8 KB ATxmega64A1-CUR ATxmega128A1-C7U ATxmega128A1-C7UR 100C2 ATxmega64A1-C7U 64K + 4K 2 KB 4 KB ATxmega64A1-C7UR Notes: 1.
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2. Pinout/Block Diagram PA5 PA4 PA3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI PQ3 PQ2 PQ1 PQ0 GND VCC PK7 PK6 PK5 PK4 PK3 PK2 PK1 Figure 2-1.
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Figure 2-2. CBGA-pinout Top view 1 2 3 4 5 6 Bottom view 7 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 2-1. CBGA-pinout.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block Diagram Figure 3-1. XMEGA A1 Block Diagram Oscillator / Crystal / Clock General Purpose I/O VBAT Power Supervision 32.
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  XMEGA A Manual  XMEGA A Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. The XMEGA A application notes contain example code and show applied use of the modules and peripherals.
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7. AVR CPU 7.1 Features  8/16-bit high performance AVR RISC Architecture   138 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in SRAM  Stack Pointer accessible in I/O memory space  Direct addressing of up to 16M Bytes of program and data memory  True 16/24-bit access to 16/24-bit I/O registers  Support for 8-, 16- and 32-bit Arithmetic  Configuration Change Protection of system critical features 7.
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Figure 7-1. Block diagram of the AVR CPU architecture. The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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7.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file.
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after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device.
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8. Memories 8.
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The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a flash memory signature rows for calibration data, device identification, serial number etc. 8.3 In-System Programmable Flash Program Memory he Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device.
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8.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
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Figure 8-2. Data Memory Map (Hexadecimal address) Byte Address ATxmega128A1 0 I/O Registers Byte Address 0 I/O Registers FFF (4 KB) FFF (4 KB) 1000 EEPROM 1000 EEPROM 17FF (2 KB) 17FF (2 KB) RESERVED RESERVED 2000 Internal SRAM 2000 Internal SRAM 3FFF (8 KB) 2FFF (4 KB) 4000 External Memory 3000 External Memory FFFFFF 8.6 ATxmega64A1 (0 to 16 MB) FFFFFF (0 to 16 MB) EEPROM XMEGA AU devices have EEPROM for nonvolatile data storage.
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8.10 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the external bus interface.
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Table 8-3. Number of Bytes and Pages in the EEPROM. Device EEPROM Page Size E2BYTE E2PAGE No of pages Size bytes ATxmega64A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64 ATxmega128A1 2 KB 32 ADDR[4:0 ADDR[10:5] 64 8.14.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space.
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9. DMAC - Direct Memory Access Controller 9.1 Features  Allows High-speed data transfer  From memory to peripheral From memory to memory  From peripheral to memory  From peripheral to peripheral   4 Channels  From 1 byte and up to 16M bytes transfers in a single transaction  Multiple addressing modes for source and destination address  Increment Decrement  Static   1, 2, 4, or 8 byte Burst Transfers  Programmable priority between channels 9.
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10. Event System 10.
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Figure 10-1. Event system block diagram. CPU / Software DMA Controller Event Routing Network clkPER Prescaler ADC AC Event System Controller Real Time Counter Timer / Counters DAC Port pins IRCOM he event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum routing latency is two peripheral clock cycles.
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11. System Clock and Clock options 11.1 Features  Fast start-up time  Safe run-time clock switching  Internal Oscillators:  32 MHz run-time calibrated RC oscillator 2 MHz run-time calibrated RC oscillator  32.768 kHz calibrated RC oscillator  32 kHz Ultra Low Power (ULP) oscillator with 1 kHz ouput   External clock options  0.
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Figure 11-1. The clock system, clock sources and clock distribution Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 Brown-out Detector System Clock Prescalers Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 11.3 0.
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11.3.2 32.768 kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 11.3.3 32.768 kHz Crystal Oscillator A 32.
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12. Power Management and Sleep Modes 12.1 Features  Power management for adjusting power consumption and functions  5 sleep modes  Idle Power-down  Power-save  Standby  Extended standby   Power reduction register to disable clock and turn off unused peripherals in active and idle modes 12.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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12.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 12.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 12.3.
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13. System Control and Reset 13.1 Features  Multiple reset sources for safe operation and device reset       Power-On Reset External Reset Watchdog Reset Brown-Out Reset PDI reset Software reset  Asynchronous reset  No running clock in the device is required for reset  Reset status register 13.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state.
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13.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 13.4.3 External Reset The external reset circuit is connected to the external RESET pin.
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13.5 WDT - Watchdog Timer 13.5.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 13.6 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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14. Interrupts and Programmable Multilevel Interrupt Controller 14.
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Program Address (Base Address) Source Interrupt Description 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x038 USARTC1_INT_base USART 1 on port C Interrupt base 0x03E AES_INT_vect AES Interrupt vector 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x0
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Program Address (Base Address) Source Interrupt Description 0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base 0x0E4 TCF1_INT_base Timer/Counter 1 on port F Interrupt base 0x0EC SPIF_INT_vector SPI ion port F Interrupt base 0x0EE USARTF0_INT_base USART 0 on port F Interrupt base 0x0F4 USARTF1_INT_base USART 1 on port F Interrupt base [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8067O–AVR–06/2013 31
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15. I/O Ports 15.
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15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3.
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15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 15-6.
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15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 35. Figure 15-7. Input sensing system overview Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O the pin value is inverted before the input sensing. 15.
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16. T/C - 16-bit Timer/Counter 16.
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The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res - High Resolution Extension” on page 39 for more details. Figure 16-1.
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17. AWeX - Advanced Waveform Extension 17.1 Features  Output with complementary output from each Capture channel  Four Dead Time Insertion (DTI) Units, one for each Capture channel  8-bit DTI Resolution  Separate High and Low Side Dead-Time Setting  Double Buffered Dead-Time  Event Controlled Fault Protection  Single Channel Multiple Output Operation (for BLDC motor control)  Double Buffered Pattern Generation 17.
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18. Hi-Res - High Resolution Extension 18.1 Features  Increases Waveform Generator resolution by 2-bits (4x)  Supports Frequency, single- and dual-slope PWM operation  Supports the AWeX when this is enabled and used for the same Timer/Counter 18.2 Overview TThe high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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19. RTC - 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator   Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.
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20. TWI - Two-Wire Interface 20.
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It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and TWIF.
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21. SPI - Serial Peripheral Interface 21.1 Features  Four identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 21.
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22. USART 22.
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23. IRCOM - IR Communication Module 23.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2Kbps  Selectable pulse modulation scheme  3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled   Built-in filtering  Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
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24. AES and DES Crypto Engine 24.1 Features  Data Encryption Standard (DES) CPU instruction  Advanced Encryption Standard (AES) crypto module  DES Instruction  Encryption and decryption DES supported  Encryption/decryption in 16 CPU clock cycles per 8-byte block   AES crypto module  Encryption and decryption Supports 128-bit keys  Supports XOR data load mode to the state memory  Encryption/decryption in 375 clock cycles per 16-byte block  24.
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25. EBI – External Bus Interface 25.1 Features  Supports SRAM up to:   512KB using 3-port EBI configuration 16MB using 3-port EBI configuration  Supports SDRAM up to:  128Mb using 3-port EBI configuration  Four software configurable chip selects  Software configurable wait state insertion  Can run from the 2x peripheral clock frequency for fast access 25.2 Overview The External Bus Interface (EBI) is used to connect external peripherals and memory for access through the data memory space.
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26. ADC - 12-bit Analog to Digital Converter 26.
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Figure 26-1. ADC overview ADC0 Compare • •• ADC7 ADC0 Internal signals VINP CH0 Result •• • ADC7 ADC4 CH1 Result Threshold (Int Req) 1x - 64x CH2 Result • •• ADC7 Int. signals < > Internal signals CH3 Result VINN ADC0 • •• ADC3 Int. signals Internal 1.00V Internal VCC/1.6V Reference Voltage AREFA AREFB Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.
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27. DAC - 12-bit Digital to Analog Converter 27.
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Each DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers. A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software.
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28. AC - Analog Comparator 28.
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Figure 28-1. Analog comparator overview Pin Input + AC0OUT Pin Input Hysteresis DAC Voltage Scaler Enable ACnMUXCTRL ACnCTRL Interrupt Mode Enable Bandgap WINCTRL Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis Pin Input + AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 28-2. Figure 28-2.
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29. Programming and Debugging 29.
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30. Pinout and Pin Functions The pinout of XMEGA A1 is shown in “Pinout/Block Diagram” on page 3. In addition to general I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time. 30.1 Alternate Pin Function Description The tables below shows the notation for all pin functions available and describes its function. 30.1.
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CLK SDRAM Clock (SDRAM) DQM Data Mask Signal/Output Enable (SDRAM) RAS Row Access Strobe (SDRAM) 2P 2 Port Interface 3P 3 Port Interface 30.1.5 Timer/Counter and AWEX functions OCnx Output Compare Channel x for Timer/Counter n OCnx Inverted Output Compare Channel x for Timer/Counter n OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 30.1.
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30.1.
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30.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. Table 30-1. Port A - Alternate functions.
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PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 PC3 18 SYNC OC0D OC0BHS PC4 19 SYNC OC0CLS OC1A PC5 20 SYNC OC0CHS OC1B PC6 21 SYNC PC7 22 SYNC USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT CLKOUT EVOUT TXD0 SS XCK1 MOSI OC0DLS RXD1 MISO OC0DHS TXD1 SCK Table 30-4. Port D - Alternate functions.
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PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 PF1 46 SYNC OC0B XCK0 PF2 47 SYNC/ASYNC OC0C RXD0 PF3 48 SYNC OC0D TXD0 PF4 49 SYNC OC1A PF5 50 SYNC OC1B PF6 51 PF7 52 USARTF1 SPIF TWIF SCL SS XCK1 MOSI SYNC RXD1 MISO SYNC TXD1 SCK Table 30-7. Port H - Alternate functions.
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Table 30-9. Port K - Alternate functions.
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31. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Table 31-1.
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Base Address Name Description 0x04A0 TWIE Two Wire Interface on port E 0x04B0 TWIF Two Wire Interface on port F 0x0600 PORTA Port A 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x06E0 PORTH Port H 0x0700 PORTJ Port J 0x0720 PORTK Port K 0x07C0 PORTQ Port Q 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x
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Base Address Name Description 0x0B40 TCF1 Timer/Counter 1 on port F 0x0B90 HIRESF High Resolution Extension on port F 0x0BA0 USARTF0 USART 0 on port F 0x0BB0 USARTF1 USART 1 on port F 0x0BC0 SPIF Serial Peripheral Interface on port F [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8067O–AVR–06/2013 64
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32.
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Mnemonics Operands Description RCALL k Relative Call Subroutine Operation Flags #Clocks PC  PC + k + 1 None 2 / 3(1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3(1) call Subroutine PC  k None 3 / 4(1) RET Subroutine Return PC  STACK None 4 / 5(1) RETI Interrupt Return PC  STACK I 4 / 5(1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Com
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Mnemonics Operands Description LDI Rd, K Load Immediate Operation Flags Rd  K #Clocks None 1 LDS Rd, k Load Direct from data space Rd  (k) None 2 LD Rd, X Load Indirect Rd  (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y  
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Mnemonics Operands Description Operation SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Flags #Clocks (RAMPZ:Z) Z   R1:R0, Z+2 None - Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1(1) Rd  STACK None 2(1) Rd(n+1) Rd(0) C    Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C    Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C
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Mnemonics Operands Description Operation Flags #Clocks None 1 None 1 MCU Control Instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Notes: 1. 2. (See specific descr. for BREAK) Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing Internal SRAM.
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33. Packaging information 33.1 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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33.2 100C1 0.12 Z E Marked A1 Identifier SIDE VIEW D A TOP VIEW A1 Øb e A1 Corner 0.90 TYP 10 9 8 7 6 5 4 3 2 1 A 0.90 TYP B C D COMMON DIMENSIONS (Unit of Measure = mm) E D1 F e SYMBOL MIN H A 1.10 – 1.20 I A1 0.30 0.35 0.40 D 8.90 9.00 9.10 G J E1 BOTTOM VIEW NOM MAX E 8.90 9.00 9.10 D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e NOTE 0.
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33.3 100C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 E1 SIDE VIEW 100 - Ø0.35 ± 0.05 J I H G e COMMON DIMENSIONS (Unit of Measure = mm) F D1 E SYMBOL MIN NOM MAX D A – – 1.00 C A1 0.20 – – B A2 0.65 – – D 6.90 7.00 7.10 A D1 1 2 3 4 5 6 7 8 9 b e BOTTOM VIEW 5.85 BSC 10 E A1 BALL CORNER NOTE 6.90 7.00 E1 b 7.10 5.85 BSC 0.30 0.35 e 0.40 0.65 BSC 12/23/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 100C2, 100-ball (10 x 10 Array), 0.
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34. Electrical Characteristics 34.1 Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . . -55C to +125C *NOTICE: Storage Temperature . . . . . . . . . . . . . -65C to +150°C Voltage on any Pin with respect to Ground-0.5V to VCC+0.5V Maximum Operating Voltage . . . . . . . . . . . . . . . . 3.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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Symbol Parameter Condition Min Typ Max Units (2) Module current consumption RC32M 395 RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source RC2M 120 RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source RC32K 155 30 PLL ICC TBD Multiplication factor = 10x 195 Watchdog normal mode TBD BOD Continuous mode 120 BOD Sampled mode 1 Internal 1.00 V ref 85 Temperature reference 80 RTC with int.
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34.3 Speed Table 34-2. Operating voltage and frequency. Symbol Parameter ClkCPU Condition CPU clock frequency Min Typ Max VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency of the XMEGA A1 devices is depending on VCC. As shown in Figure 34-1 on page 75 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 34-1. Maximum Frequency vs. Vcc MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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34.4 Flash and EEPROM Memory Characteristics Table 34-3. Endurance and data retention. Symbol Parameter Condition Min 25°C 10K 85°C 10K 25°C 100 55°C 25 25°C 80K 85°C 30K 25°C 100 55°C 25 Typ Max Write/Erase cycles Units Cycle Flash Data retention Year Write/Erase cycles Cycle EEPROM Data retention Year Table 34-4. Programming time. Symbol Parameter Condition Chip Erase (2) Flash, EEPROM Flash EEPROM Notes: 1. 2. 34.
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Symbol Parameter Condition Conversion rate VCC<2.0V 500 RES = 8 or 12, GAIN = 0 or 1 Sampling Time 1/2 ADCclk cycle Input bandwidth INT1V 5 7 8 0.25 Conversion range Reference voltage Units ksps (propagation delay) VREF Max 2000 (RES+2)/2+GAIN Analog Supply Voltage Typ VCC2.0V Conversion time AVCC Min ADCclk cycles µS 0 VREF V Vcc-0.3 Vcc+0.3 V 1.0 Vcc-0.6 V VCC2.0V 2000 VCC<2.0V 500 kHz Internal 1.00V reference 1.00 V INTVCC Internal VCC/1.6 VCC/1.
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34.6 DAC Characteristics Table 34-7. DAC characteristics. Symbol Parameter Condition INL Integral Non-Linearity VCC = 1.6-3.6V DNL Differential Non-Linearity VCC = 1.6-3.6V Fclk Min VREF = Ext. ref 5 VREF = Ext. ref 0.6 VREF= AVCC 0.6 Max Units LSB <±1 LSB Conversion rate AREF External reference voltage 1.1 Reference input impedance 34.7 Typ 1000 ksps AVCC-0.6 V >10 M Max output voltage Rload=100k AVCC*0.98 V Min output voltage Rload=100k 0.
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Symbol Parameter Condition Min T= 85°C, After calibration Typ Max 0.99 Units 1.01 ADC/DAC ref V 1 Variation over voltage and temperature 34.9 VCC = 1.6 - 3.6V, T = -40C to 85C ±5 % Brownout Detection Characteristics Table 34-10. Brownout Detection characteristics. Symbol Parameter Condition Min Typ BOD level 0 falling Vcc 1.6 BOD level 1 falling Vcc 1.9 BOD level 2 falling Vcc 2.1 BOD level 3 falling Vcc 2.4 BOD level 4 falling Vcc 2.6 BOD level 5 falling Vcc 2.
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Symbol VOH Parameter Output High Voltage GPIO Condition Min Typ IOH = -8 mA, VCC = 3.3V 2.6 3 IOH = -6 mA, VCC = 3.0V 2.1 2.2 IOH = -2 mA, VCC = 1.8V 1.4 1.6 Max Units V IIL Input Leakage Current I/O pin <0.001 1 µA IIH Input Leakage Current I/O pin <0.001 1 µA RP I/O pin Pull/Buss keeper Resistor 20 k Reset pin Pull-up Resistor 20 k Input hysteresis 0.5 V RRST 34.11 POR Characteristics Table 34-12. Power-on Reset characteristics.
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Table 34-15. Internal 2MHz oscillator characteristics. Symbol Parameter Condition Accuracy T = 85C, VCC = 3V, After production calibration DFLL Calibration step size T = 25C, VCC = 3V Min Typ -1.5 Max Units 1.5 % 0.175 % Table 34-16. Internal 32MHz oscillator characteristics. Symbol Parameter Condition Accuracy T = 85C, VCC = 3V, After production calibration DFLL Calibration stepsize T = 25C, VCC = 3V Min Typ -1.5 Max Units 1.5 % 0.2 % Table 34-17.
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35. Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency fSYS = 1 - 32 MHz, T = 25°C 25 3.3V 20 Icc [mA] 3.0V 2.7V 15 10 2.2V 5 1.8V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 35-2. Active Supply Current vs. VCC fSYS = 1.0 MHz 1200 85°C -40°C 25°C 1000 Icc [uA] 800 600 400 200 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Idle Supply Current Figure 35-3. Idle Supply Current vs. Frequency fSYS = 1 - 32 MHz, T = 25°C , 10 3.3V 9 8 3.0V 7 2.7V Icc [mA] 6 5 4 3 2.2V 2 1.8V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 35-4. Active Supply Current vs. VCC fSYS = 1.0 MHz 400 85°C 25°C -40°C 350 300 250 Icc [uA] 35.2 200 150 100 50 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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35.3 Power-down Supply Current Figure 35-5. Power-down Supply Current vs. Temperature 2.5 3.3V 3.0V 2.7V 2.2V 1.8V 2 Icc [uA] 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Power-save Supply Current Figure 35-6. Power-save Supply Current vs. Temperature Sampled BOD, WDT, RTC from ULP enabled 3.5 3.3V 2.7V 3 2.2V 1.8V 2.5 Icc [uA] 35.4 2 1.5 1 0.
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Pin Pull-up Figure 35-7. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 100 Ireset [uA] 80 60 -40 °C 40 85 °C 25 °C 20 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 vreset [V] Figure 35-8. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.0V 180 160 140 120 Ireset [uA] 35.5 100 80 60 -40 °C 85 °C 40 25 °C 20 0 0 0.5 1 1.5 2 2.
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Figure 35-9. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.3V 180 160 140 Ireset [uA] 120 100 80 -40 °C 85 °C 60 40 20 25 °C 0 0 0.5 1 1.5 2 2.5 3 vreset [V] Pin Thresholds and Hysteresis Figure 35-10.I/O Pin Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” 2.5 -40 °C 25 °C 85 °C 2 Vthreshold [V] 35.6 1.5 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 35-11.I/O Pin Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” 1.8 85 °C 25 °C -40 °C 1.6 1.4 Vthreshold [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 35-12.I/O Pin Input Hysteresis vs. VCC. 0.8 Vthreshold [V] 0.6 85 °C 25 °C -40 °C 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 35-13.Reset Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” 1.8 -40 °C 25 °C 85 °C 1.6 1.4 Vthreshold [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 35-14.Reset Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” 1.8 -40 °C 25 °C 85 °C 1.6 1.4 Vthreshold [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Bod Thresholds Figure 35-15.BOD Thresholds vs. Temperature BOD Level = 1.6V 1.638 1.632 Rising Vcc VBOT [V] 1.626 1.62 1.614 Falling Vcc 1.608 1.602 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 40 50 60 70 80 90 Temperature [°C] Figure 35-16.BOD Thresholds vs. Temperature BOD Level = 2.9V 3.01 Rising Vcc 2.995 2.98 VBOT [V] 35.7 2.965 2.95 2.935 Falling Vcc 2.92 2.
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35.8 Bandgap Figure 35-17.Internal 1.00V Reference vs. Temperature. 1.004 1.0035 1.003 VREF [V] 1.0025 1.002 1.0015 1.001 1.0005 1 3.0V 1.8V 0.9995 0.999 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Analog Comparator Figure 35-18.Analog Comparator Hysteresis vs. VCC High-speed, Small hysteresis 30 25 Hysteresis [mV] 35.9 25°C 20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 35-19.Analog Comparator Hysteresis vs. VCC, High-speed Large hysteresis 60 50 Hysteresis [mV] 25°C 40 30 20 10 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 35-20.Analog Comparator Propagation Delay vs. VCC High-speed 120 Propagation Delay [ns] 100 80 60 25°C 40 20 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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35.10 Oscillators and Wake-up Time Figure 35-21.Internal 32.768 kHz Oscillator Frequency vs. Temperature 1.024 kHz output p 1.03 1.025 1.8 V 1.02 3.0 V f [kHz] 1.015 1.01 1.005 1 0.995 0.99 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 T [°C] Figure 35-22.Ultra Low-Power (ULP) Oscillator Frequency vs. Temperature 1 kHz output p 0.93 0.92 f1kHz output [kHz] 0.91 0.9 3.0 V 0.89 1.8 V 0.88 0.
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Figure 35-23.Internal 2 MHz Oscillator CalA Calibration Step Size T = -40 to 85C, VCC = 3V 0.006 Step size: f [MHz] 0.005 0.004 0.003 0.002 0.001 0 0 20 40 60 80 100 120 140 60 70 CALA [LSB] Figure 35-24.Internal 2 MHz Oscillator CalB Calibration Step Size T = -40 to 85C, VCC = 3V 0.04 0.035 Step size: f [MHz] 0.03 0.025 0.02 0.015 0.01 0.
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Figure 35-25.Internal 32 MHz Oscillator CalA Calibration Step Size T = -40 to 85C, VCC = 3V 0.09 0.08 Step size: f [MHz] 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 20 40 60 80 100 120 140 60 70 CALA Figure 35-26.Internal 32 MHz Oscillator CalB Calibration Step Size T = -40 to 85C, VCC = 3V 0.7 0.6 Step size: f [MHz] 0.5 0.4 0.3 0.2 0.
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35.11 PDI Speed Figure 35-27.PDI Speed vs. VCC 35 25 °C 30 fMAX [MHz] 25 20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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36. Errata 36.1 ATxmega64A1and ATxmega128A1 rev. H  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  The ADC has up to ±2 LSB inaccuracy  ADC gain stage output range is limited to 2.4 V  Sampling speed limited to 500 ksps for supply voltage below 2.0V  ADC Event on compare match non-functional  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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 TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag erroneously read as set  WDR instruction inside closed window will not issue reset 1.
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Problem fix/Workaround None, the actual ADC resolution will be reduced with up to ±2 LSB. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: – 1x gain: 2.4 V – 2x gain: 1.2 V – 4x gain: 0.
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None. 8. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 9.
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Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 13. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 14.
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18. DAC has up to ±10 LSB noise in Sampled Mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 19.
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Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 24. Pin configuration does not affect Analog Comparator Output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output function.
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Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 29. Some NVM Commands are non-functional The following NVM commands are non-functional: – 0x2B Erase Flash Page – 0x2E Write Flash Page – 0x2F Erase & Write Flash Page – 0x3A Flash Range CRC Problem fix/Workaround None for Flash Range CRC Use separate programming commands for accessing application and boot section.
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32. Accessing EBI address space with PREBI set will lock Bus Master If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could result in bus hang-up, blocking all further access to all data memory. Problem fix/Workaround Ensure that EBI is disabled before setting EBI Power Reduction bit. 33.
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37. TWI, a general address call will match independent of the R/W-bit value When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address match regardless of the received R/W bit. Problem fix/Workaround Use software to check the R/W-bit on general call address match. 38. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start.
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40. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 41. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
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36.2 ATxmega64A1 and ATxmega128A1 rev. G  Bootloader Section in Flash is non-functional  Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously  DAC is nonlinear and inaccurate when reference is above 2.4V  ADC gain stage output range is limited to 2.
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 ±200 LSB for Sample and Hold mode Problem fix/Workaround None, avoid using a voltage reference above 2.4V. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: – 1x gain: 2.4 V – 2x gain: 1.2 V – 4x gain: 0.
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7. TWI, the minimum I2C SCL low time could be violated in Master Read mode When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will immediately release the SCL line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the I2C specification could be violated. Problem fix/Workaround If this causes a potential problem in the application, software must ensure that the Repeated Start is never issued before one SCL low time has passed. 8.
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12. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC and DAC. Problem fix/Workaround If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set in sampled mode. 13.
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17. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workarund When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 18.
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37. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 8067O – 06/2013 1. 37.2 37.3 8067N – 03/2013 1. Removed all references to ATxmega192A1, ATxmega256A1 and ATxmega384A1. 2. Updated module description. Based on the XMEGA A1U device datasheet. 3. Updated analog comparator (AC) overview, Figure 28-1 on page 53. 4.
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37.5 6. Updated “DAC Characteristics” on page 78. Removed DC output impedance. 7. Fixed typo in “Packaging information” section. 8. Fixed typo in “Errata” section. 8067K – 02/2010 1. 37.6 37.7 37.8 Added “PDI Speed vs. VCC” on page 95. 8067J – 02/2010 1. Removed JTAG Reset from the datasheet. 2. Updated “Timer/Counter and AWEX functions” on page 56. 3. Updated “Alternate Pin Functions” on page 58. 3. Updated all “Electrical Characteristics” on page 73. 4.
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37.9 8067G – 11/2008 1. Updated “Block Diagram” on page 6. 2. Updated feature list in “Memories” on page 12. 3. Updated “Programming and Debugging” on page 54. 4. Updated “Peripheral Module Address Map” on page 62. IRCOM has address 0x8F0. 5. Added “Electrical Characteristics” on page 73. 6. Added “Typical Characteristics” on page 82. 7. Added “ATxmega64A1and ATxmega128A1 rev. H” on page 96. 8. Updated “ATxmega64A1 and ATxmega128A1 rev. G” on page 107. 37.10 8067F – 09/2008 1.
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37.13 8067C – 06/2008 1. Updated the Front page and “Features” on page 1. 2. Updated the “DC Characteristics” on page 73. 3. Updated Figure 3-1 on page 6. 4. Added “Flash and EEPROM Page Size” on page 15. 5. Updated Table 33-6 on page 72 with new data: Gain Error, Offset Error and Signal -to-Noise Ratio (SNR). 6. Updated Errata “ATxmega64A1 and ATxmega128A1 rev. G” on page 107. 37.14 8067B – 05/2008 1. Updated “Pinout/Block Diagram” on page 3 and “Pinout and Pin Functions” on page 55. 2.
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[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8067O–AVR–06/2013 116
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11.3 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 24 12.1 12.2 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Sleep Modes . . . . . . . . . . . . . . . . . . . . .
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22.1 22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23. IRCOM - IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 45 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overview . . . . . . . . . . . . . . . . . . . .
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34.10 34.11 34.12 34.13 PAD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 80 80 80 35. Typical Characteristics . . . . . . .
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[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8067O–AVR–06/2013 5
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.