Datasheet

49
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
Figure 26-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be
sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results will be
available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5
µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
CH1 Result
CH0 Result
CH2 Result
Compare
<
>
Threshold
(Int Req)
Internal 1.00V
Internal VCC/1.6V
AREFA
AREFB
V
INP
V
INN
Internal
signals
Internal
signals
CH3 Result
ADC0
ADC7
ADC4
ADC7
ADC0
ADC3
•
•
•
Int. signals
Int. signals
Reference
Voltage
1x - 64x
•
•
•
•
•
•
ADC0
ADC7
•
•
•