Datasheet

6
XMEGA C4 [DATASHEET]
8493G–AVR–01/2014
3.1 Block Diagram
Figure 3-1. XMEGA C4 block diagram.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (4)
SRAM
ADCA
ACA
OCD
Int. Refs.
PDI
PA[0..7]
PB[0..3]
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
Sleep
Controller
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PE[0..3]
PORT D (8)
TCD0
USARTD0
SPID
TCE0
TWIE
PORT E (4)
Tempref
VCC/10
PORT R (2)
XTAL1/
TOSC1
XTAL2/
TOSC2
PR[0..1]
DATA BUS
NVM Controller
M
O
RPEEhsalF
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
To Clock
Generator
EVENT ROUTING NETWORK
USB
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I /O
Ground
Power