Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 44 (7x7) 8/16-Bit 32 MHz I/O number 34

8493G–AVR–01/2014

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 16K - 32KBytes of In-System Self-Programmable Flash

 4KBytes Boot Code Section with Independent Lock Bits

 1KBytes EEPROM

 2K - 4KBytes Internal SRAM

 Peripheral features

 Four-channel event system

 Four 16-bit timer/counters

 Three timer/counters with four output compare or input capture channels

 One timer/counter with two output compare or input capture channels

 High resolution extension on two timer/counters

 Advanced waveform extension (AWeX) on one timer/counter

 One USB device interface

 USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant

 32 Endpoints with full configuration flexibility

 Three USARTs with IrDA support for one USART

 Two two-wire interfaces with dual address match (I

C and SMBus compatible)

 Two serial peripheral interfaces (SPIs)

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE

802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter

 Two Analog Comparators with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interface

 PDI (program and debug interface)

 I/O and packages

 34 programmable I/O pins

 44-lead TQFP

 44-pad QFN

 49-ball VFBGA

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA C4 Microcontroller

ATxmega32C4

ATxmega16C4

Summary of content (189 pages)

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8/16-bit Atmel XMEGA C4 Microcontroller ATxmega32C4 ATxmega16C4 Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories          16K - 32KBytes of In-System Self-Programmable Flash 4KBytes Boot Code Section with Independent Lock Bits 1KBytes EEPROM 2K - 4KBytes Internal SRAM Peripheral features  Four-channel event system  Four 16-bit timer/counters  Three timer/counters with four output compare or input capture channels 
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1.
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2. Pinout/Block Diagram PA4 PA3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET_PDI PDI 44 43 42 41 40 39 38 37 36 35 34 Figure 2-1. Block diagram and pinout. Programming, debug, test Power Ground External clock /Crystal pins General Purpose I /O Digital function Analog function /Oscillators Port R GND 8 VCC 9 PC0 10 PC1 11 Event System Controller CRC OCD Prog/Debug Interface AC0:1 Interrupt Controller AREF BUS matrix Internal references SRAM FLASH 1. 2.
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Figure 2-2.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block Diagram Figure 3-1. XMEGA C4 block diagram. PR[0..1] XTAL1/ TOSC1 Programming, debug, test Power Ground Digital function Analog function /Oscillators External clock /Crystal pins General Purpose I /O XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  Atmel AVR XMEGA C manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA C manual describes the modules and peripherals in depth.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   142 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
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7. Memories 7.
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device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash program memory (Hexadecimal address).
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The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes. Device 7.3.
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7.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 15. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. Figure 7-2. Data memory map (hexadecimal address).
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7.10 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.
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8. Event System 8.
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9. System Clock and Clock options 9.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators:  32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output   External clock options  0.4MHz - 16MHz crystal oscillator 32.
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Figure 9-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB System Clock Prescalers Brown-out Detector Prescaler Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32kHz Int. ULP 32.768kHz Int. OSC 32.768kHz TOSC 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 9.3 0.
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9.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 9.3.3 32.768kHz Crystal Oscillator A 32.
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10. Power Management and Sleep Modes 10.1 Features  Power management for adjusting power consumption and functions  Five sleep modes  Idle Power down  Power save  Standby  Extended standby   Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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10.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 10.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 10.3.
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11. System Control and Reset 11.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 11.
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11.4 Reset Sources 11.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. 11.4.
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12. WDT – Watchdog Timer 12.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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13. Interrupts and Programmable Multilevel Interrupt Controller 13.
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Table 13-1. Reset and interrupt vectors.
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14. I/O Ports 14.
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14.3 Output Driver All port pins (Pxn) have programmable output configuration. 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole. DIRxn OUTxn Pxn INxn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input). DIRxn OUTxn Pxn INxn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input).
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14.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 14-4. I/O configuration - Totem-pole with bus-keeper. DIRxn OUTxn Pxn INxn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down. OUTxn Pxn INxn Figure 14-6. I/O configuration - Wired-AND with optional pull-up.
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14.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7. Figure 14-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.
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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 15.
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Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers.
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16. TC2 – Timer/Counter Type 2 16.
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17. AWeX – Advanced Waveform Extension 17.
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18. Hi-Res – High Resolution Extension 18.1 Features  Increases waveform generator resolution up to 8x (three bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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19. RTC – 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator   Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.
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20. USB – Universal Serial Bus Interface 20.1 Features  One USB 2.0 full speed (12Mbps) and low speed (1.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB.
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21. TWI – Two-Wire Interface 21.
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22. SPI – Serial Peripheral Interface 22.1 Features  Two Identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 22.
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23. USART 23.
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24. IRCOM – IR Communication Module 24.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2Kbps  Selectable pulse modulation scheme  3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled   Built-in filtering  Can be connected to and used by any USART 24.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
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25. CRC – Cyclic Redundancy Check Generator 25.1 Features  Cyclic redundancy check (CRC) generation and checking for  Communication data Program or data in flash memory  Data in SRAM and I/O memory space   Integrated with flash memory, and CPU   Automatic CRC of the complete or a selectable range of the flash memory CPU can load data to the CRC generator through the I/O interface  CRC polynomial software selectable to   CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.
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26. ADC – 12-bit Analog to Digital Converter 26.1 Features  One Analog to Digital Converter (ADC)  12-bit resolution  Up to 300 thousand samples per second   Down to 2.3µs conversion time with 8-bit resolution Down to 3.
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Figure 26-1. ADC overview. ADC0 • • • ADC11 Compare Register ADC Internal signals ADC0 • • • ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding.
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27. AC – Analog Comparator 27.
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Figure 27-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis Enable Voltage Scaler ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 27-2. Figure 27-2. Analog comparator window function.
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28. Programming and Debugging 28.
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29. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 29.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 29.1.
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SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB 29.1.6 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 29.1.
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29.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 29-1. Port A - Alternate functions.
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USARTC0 PORT C PIN# INTERRUPT PC5 15 PC6 PC7 Notes: 1. 2. 3. 4. 5. 6. USART C1 SPIC(4) XCK1 MOSI OC0DLS RXD1 MISO clkRTC OC0DHS TXD1 SCK clkPER TCC0(1)(2) AWEXC TCC1 SYNC OC0CHS OC1B 16 SYNC 17 SYNC (3) TWIC CLOCK OUT(5) EVENT OUT(6) EVOUT Pin mapping of all TC0 can optionally be moved to high nibble of port. If TC0 is configured as TC2 all eight pins can be used for PWM output. Pin mapping of all USART0 can optionally be moved to high nibble of port.
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30. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA C4. For complete register description and summary for each peripheral module, refer to the XMEGA C manual. Table 30-1. Peripheral module address map.
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Base address Name Description 0x0660 PORTD Port D 0x0680 PORTE Port E 0x07E0 PORTR Port R 0x0800 TCC0 Timer/counter 0 on port C 0x0840 TCC1 Timer/counter 1 on port C 0x0880 AWEXC Advanced waveform extension on port C 0x0890 HIRESC High resolution extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08B0 USARTC1 USART 1 on port C 0x08C0 SPIC 0x08F8 IRCOM 0x0900 TCD0 0x09A0 USARTD0 0x09C0 SPID Serial peripheral interface on port D 0x0A00 TCE0 Timer/counter 0 on por
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31.
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Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3(1) call Subroutine PC  k None 3 / 4(1) RET Subroutine Return PC  STACK None 4 / 5(1) RETI Interrupt Return PC  STACK I 4 / 5(1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry
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Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd  (k) None 2(1)(2) LD Rd, X Load Indirect Rd  (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y+1 None 1(1)(2) LD Rd, -Y Load Indirect
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Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1(1) Pop Register from Stack Rd  STACK None 2(1) Z, Rd Exchange RAM location Temp Rd (Z)    Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z)    Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp Rd
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Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr.
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32. Packaging information 32.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
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32.
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32.
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33. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 33.1 ATxmega16C4 33.1.1 Absolute Maximum Ratings Stresses beyond those listed in Table 33-1 under may cause permanent damage to the device.
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The maximum CPU clock frequency depends on VCC. As shown in Figure 33-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 33-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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33.1.3 Current consumption Table 33-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk Min. Power-down power consumption 40 VCC = 3.0V 80 VCC = 1.8V 200 VCC = 3.0V 410 VCC = 1.8V 350 600 0.75 1.4 7.5 12 VCC = 3.
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Table 33-5. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 0.8 32.768kHz int. oscillator 29 Max. Units 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 245 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 410 20x multiplication factor, 32MHz int. osc. DIV4 as reference 290 Watchdog timer µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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33.1.4 Wake-up time from sleep modes Table 33-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 5.0 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max.
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33.1.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 33-7. I/O pin characteristics. Symbol Parameter Condition Min. Typ. Max. Units -20 20 mA VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5 VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VCC = 2.4- 3.6V -0.5 0.3*VCC VCC = 1.6 - 2.4V -0.5 0.
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33.1.6 ADC characteristics Table 33-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.
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Table 33-10. Accuracy characteristics. Symbol RES Condition(2) Parameter Resolution 12-bit resolution Differential mode INL(1) Integral non-linearity Min. Typ. Max. Differential 8 12 12 Single ended signed 7 11 11 Single ended unsigned 8 12 12 16ksps, VREF = 3V 0.5 1 16ksps, all VREF 0.8 2 300ksps, VREF = 3V 0.6 1 1 2 16ksps, VREF = 3.0V 0.5 1 16ksps, all VREF 1.3 2 16ksps, VREF = 3V 0.3 1 16ksps, all VREF 0.5 1 300ksps, VREF = 3V 0.35 1 300ksps, all VREF 0.
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Table 33-11. Gain stage characteristics. Rin Input resistance Switched in normal mode 4.0 k Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock rate Same as ADC 100 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 10 0.
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33.1.8 Bandgap and Internal 1.0V Reference Characteristics Table 33-13. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Calibrated at T= 85°C, VCC = 3.0V 0.98 1 1.02 ±1.0 % 33.1.9 Brownout Detection Characteristics Table 33-14.
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33.1.11 Power-on Reset Characteristics Table 33-16. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 1.3 Max. Units V 1.59 VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 33.1.12 Flash and EEPROM Memory Characteristics Table 33-17. Endurance and data retention.
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33.1.13 Clock and Oscillator Characteristics 33.1.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 33-19. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 33.1.13.2Calibrated 2MHz RC Internal Oscillator characteristics Table 33-20. 2MHz internal oscillator characteristics.
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33.1.13.5Internal Phase Locked Loop (PLL) characteristics Table 33-23. Internal PLL characteristics. Symbol fIN Parameter Input frequency Output frequency (1) fOUT Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 33.1.
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Table 33-25. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
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Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Max. Units pF 33.1.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 33-27. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) Typ. 60 Crystal load capacitance 9.
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33.1.14 SPI Characteristics Figure 33-5. SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 33-6. SPI timing requirements in slave mode.
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Table 33-28. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA C Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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Table 33-29. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7*VCC VCC+0.5 VIL Input low voltage -0.5 0.
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33.2 ATxmega32C4 33.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 33-30 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 33-30. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
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Figure 33-8. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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33.2.3 Current consumption Table 33-33. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk Min. Power-down power consumption 40 VCC = 3.0V 80 VCC = 1.8V 200 VCC = 3.0V 410 VCC = 1.8V 350 600 0.75 1.4 7.5 12 VCC = 3.
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Table 33-34. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 0.8 32.768kHz int. oscillator 29 Max. Units 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 245 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 410 20x multiplication factor, 32MHz int. osc. DIV4 as reference 290 Watchdog timer µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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33.2.4 Wake-up time from sleep modes Table 33-35. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 5.0 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max.
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33.2.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 33-36. I/O pin characteristics. Symbol Parameter Condition Min. Typ. Max. Units -20 20 mA VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5 VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VCC = 2.4- 3.6V -0.5 0.3*VCC VCC = 1.6 - 2.4V -0.5 0.
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33.2.6 ADC characteristics Table 33-37. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.
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Table 33-39. Accuracy characteristics. Symbol RES Condition(2) Parameter Resolution 12-bit resolution Differential mode INL(1) Integral non-linearity Min. Typ. Max. Differential 8 12 12 Single ended signed 7 11 11 Single ended unsigned 8 12 12 16ksps, VREF = 3V 0.5 1 16ksps, all VREF 0.8 2 300ksps, VREF = 3V 0.6 1 1 2 16ksps, VREF = 3.0V 0.5 1 16ksps, all VREF 1.3 2 16ksps, VREF = 3V 0.3 1 16ksps, all VREF 0.5 1 300ksps, VREF = 3V 0.35 1 300ksps, all VREF 0.
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Table 33-40. Gain stage characteristics. Rin Input resistance Switched in normal mode 4.0 k Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock rate Same as ADC 100 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 10 0.
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33.2.8 Bandgap and Internal 1.0V Reference Characteristics Table 33-42. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Calibrated at T= 85°C, VCC = 3.0V 0.98 1 1.02 ±1.0 % 33.2.9 Brownout Detection Characteristics Table 33-43.
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33.2.11 Power-on Reset Characteristics Table 33-45. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 33.2.12 Flash and EEPROM Memory Characteristics Table 33-46.
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33.2.13 Clock and Oscillator Characteristics 33.2.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 33-48. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 33.2.13.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 33-49. 2MHz internal oscillator characteristics.
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33.2.13.5 Internal Phase Locked Loop (PLL) characteristics Table 33-52. Internal PLL characteristics. Symbol fIN Parameter Input frequency Output frequency(1) fOUT Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 33.2.
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Table 33-54. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
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Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Max. Units pF 33.2.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 33-56. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) Typ. 60 Crystal load capacitance 9.
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33.2.14 SPI Characteristics Figure 33-12. SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 33-13. SPI timing requirements in slave mode.
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Table 33-57. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA C Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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Table 33-58. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7*VCC VCC+0.5 VIL Input low voltage -0.5 0.
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34. Typical Characteristics 34.1 ATxmega16C4 34.1.1 Current consumption 34.1.1.1 Active mode supply current Figure 34-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 600 550 3.6V 500 Icc [µA] 450 400 3.0V 350 2.7V 300 250 2.2V 200 1.8V 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 34-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.6V 9 8 3.0V Icc [mA] 7 2.7V 6 5 4 2.
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Figure 34-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 180 160 -40°C Icc [µA] 140 25°C 85°C 105°C 120 100 80 60 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 600 -40°C 25°C 85°C 105°C 550 500 Icc [µA] 450 400 350 300 250 200 150 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1350 1200 -40°C 25 °C 85°C 105°C 1050 Icc [µA] 900 750 600 450 300 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.0 -40°C 25 °C 85°C 105°C 4.5 4.0 Icc [mA] 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 -40 °C 11.5 11.0 25 °C 10.5 85 °C 105°C 10.0 Icc [mA] 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 34.1.1.2 Idle mode supply current Figure 34-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 120 3.6V 105 90 3.0V ICC[uA] 75 2.7V 60 2.2V 45 1.8V 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 34-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.6 3.6V 3.2 Icc [mA] 2.8 3.0V 2.4 2.7V 2.0 1.6 1.2 2.2V 0.8 1.8V 0.4 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frenquecy [MHz] Figure 34-10.Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35.50 105°C 34.75 34.00 33.25 32.50 Icc [µA] 31.75 85°C 31.00 -40°C 30.25 25 °C 29.50 28.75 28.00 27.25 26.50 25.75 25.00 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 34-11.Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 130 105°C 85 °C 25 °C -40°C 120 110 100 Icc [µA] 90 80 70 60 50 40 30 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-12.Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 330 -40°C 25°C 85 °C 105 °C 310 290 270 Icc [µA] 250 230 210 190 170 150 130 110 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-13.Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1600 -40 °C 25 °C 85°C 105°C 1500 1400 1300 Icc [µA] 1200 1100 1000 900 800 700 600 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-14.Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 4.25 -40°C 4.00 25 °C 85°C 105°C 3.75 Icc [mA] 3.50 3.25 3.00 2.75 2.50 2.25 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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34.1.1.3 Power-down mode supply current Figure 34-15.Power-down mode supply current vs. VCC. All functions disabled. 5.5 105°C 5.0 4.5 4.0 Icc [µA] 3.5 3.0 2.5 2.0 85°C 1.5 1.0 0.5 25°C -40°C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-16.Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 6.5 105°C 6.0 5.5 5.0 Icc [µA] 4.5 4.0 3.5 85°C 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-17.Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7.5 7.0 3.6V 6.5 3.0V 2.7V 2.2V 1.8V 6.0 5.5 Icc [µA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 34.1.1.4 Power-save mode supply current Figure 34-18.Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.
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34.1.1.5 Standby mode supply current Figure 34-19.Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.1 105°C 10.9 9.7 85°C I CC [µA] 8.5 25°C -40°C 7.3 6.1 4.9 3.7 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-20.Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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34.1.2 I/O Pin Characteristics 34.1.2.1 Pull-up Figure 34-21.I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 IPIN [µA] 48 40 32 24 -40°C 25°C 85°C 105°C 16 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 34-22.I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 -40°C 25°C 85°C 105°C 24 12 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.
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Figure 34-23.I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 VPIN [V] 34.1.2.2 Output Voltage vs. Sink/Source Current Figure 34-24. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 85°C 105°C 25°C -40°C 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.
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Figure 34-25. I/O pin output voltage vs. source current. VCC = 3.0V. 3.15 2.80 2.45 VPIN [V] 2.10 1.75 1.40 1.05 25°C -40°C 85°C 105°C 0.70 0.35 0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 34-26. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.15 2.8 VPIN [V] 2.45 2.1 1.75 1.4 1.05 0.7 25°C -40°C 85°C 105°C 0.
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Figure 34-27. I/O pin output voltage vs. source current. 4 VPIN [V] 3.65 3.3 3.6V 3.3V 2.95 3.0V 2.7V 2.6 2.25 1.9 1.8V 1.6V 1.55 1.2 0.85 0.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 34-28. I/O pin output voltage vs. sink current. VCC = 1.8V. 1 0.9 0.8 105°C VPIN [V] 0.7 25°C 85°C -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 34-29. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.1 105°C 85°C 1.0 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 34-30. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1 0.9 105°C 85°C 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 34-31. I/O pin output voltage vs. sink current. 1.5 1.8V 1.6V 1.35 2.7V 3.0V 3.3V 3.6V 1.2 VPIN [V] 1.05 0.9 0.75 0.6 0.45 0.3 0.15 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 34.1.2.3 Thresholds and Hysteresis Figure 34-32.I/O pin input threshold voltage vs. VCC. T = 25C. 1.8 VIH Vthreshold [V] 1.7 1.6 VIL 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-33. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85 °C 105 °C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-34. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. ,p 1.75 -40°C 25°C 85 °C 105 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-35. I/O pin input hysteresis vs. VCC. 0.42 0.39 -40°C Vthreshold [V] 0.36 0.33 0.3 25°C 0.27 0.24 85°C 0.21 105°C 0.18 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 34.1.3 ADC Characteristics Figure 34-36. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 34-37. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 34-38. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 34-39. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 34-40. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.
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Figure 34-41.DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 34-42. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 300ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 34-43. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-44. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 34-45. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 0 -2 Gain error [mV] Single-ended signed mode -4 -6 Differential mode -8 -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-46. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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34.1.4 Analog Comparator Characteristics Figure 34-47. Analog comparator hysteresis vs. VCC. High speed, small hysteresis. VHYST [mV] 14 13 105°C 12 85°C 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-48. Analog comparator hysteresis vs. VCC. High speed, large hysteresis. 32 105°C 85°C 30 VHYST [mV] 28 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-49. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 30 28 105°C 85°C VHYST [mV] 26 24 25°C 22 -40°C 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-50. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 68 64 105°C 85°C 60 VHYST [mV] 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 34-51. Analog comparator current source vs. calibration value. T = 25C. 8 ICURRENTSOURCE [µA] 7.25 6.5 5.75 5 3.6V 4.25 3.0V 3.5 2.2V 2.75 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..0] Figure 34-52. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.6 ICURRENTSOURCE [µA] 6.2 5.8 5.4 5.0 4.6 4.2 -40°C 25°C 85°C 105°C 3.8 3.4 3.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..
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Figure 34-53. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 34.1.5 Internal 1.0V reference Characteristics Bandgap Voltage [V] Figure 34-54. ADC Internal 1.0V reference vs. temperature. 1.0088 1.008 1.0072 1.0064 1.0056 1.0048 1.004 1.0032 1.0024 1.0016 1.0008 1 0.9992 0.9984 0.9976 0.9968 1.8V 2.2V 2.7V 3.0V 3.
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34.1.6 BOD Characteristics Figure 34-55. BOD thresholds vs. temperature. BOD level = 1.6V. 1.574 Rising Vcc 1.57 Falling Vcc 1.566 VBOT [V] 1.562 1.558 1.554 1.55 1.546 1.542 1.538 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 95 105 Temperature [°C] Figure 34-56. BOD thresholds vs. temperature. BOD level = 3.0V. 2.992 2.984 Rising Vcc 2.976 VBOT [V] 2.968 2.96 2.952 2.944 Falling Vcc 2.936 2.928 2.
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34.1.7 External Reset Characteristics Figure 34-57. Minimum Reset pin pulse width vs. VCC. 145 140 135 130 TRST [ns] 125 120 115 110 105 105°C 85°C 100 95 25°C -40°C 90 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-58. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 72 64 IRESET [µA] 56 48 40 32 24 16 -40°C 25°C 85°C 105°C 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 34-59. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 34-60. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 34-61. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. -40°C 25°C 85°C 105°C 2.10 2.00 1.90 1.80 V threshold [V] 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-62. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.7 -40°C 25°C 85 °C 105 °C 1.6 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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34.1.8 Power-on Reset Characteristics I CC [µA] Figure 34-63. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 500 85°C 105°C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 34-64. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40°C 585 520 25°C 85°C 105°C I CC [µA] 455 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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34.1.9 Oscillator Characteristics 34.1.9.1 Ultra Low-Power internal oscillator Frequency [kHz] Figure 34-65.Ultra Low-Power internal oscillator frequency vs. temperature. 35.4 35.1 34.8 34.5 34.2 33.9 33.6 33.3 33.0 32.7 32.4 32.1 31.8 31.5 31.2 30.9 3.6V 3.3V 3.0V 2.7V 2.0V 1.8V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 34.1.9.2 32.768kHz Internal Oscillator Figure 34-66. 32.768kHz internal oscillator frequency vs. temperature. 32.9 3.6V 3.3V 3.0V 2.7V 2.
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Figure 34-67. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 51 3.0V 47 Frequency [kHz] 43 39 35 31 27 23 19 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL [7..0] 34.1.9.3 2MHz Internal Oscillator Figure 34-68. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 1.96 1.
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Figure 34-69. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.012 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.008 Frequency [MHz] 2.004 2.00 1.996 1.992 1.988 1.984 1.98 1.976 1.972 1.968 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Step Size [%] Figure 34-70. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.
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34.1.9.4 32MHz Internal Oscillator Figure 34-71. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.45 36 Frequency [MHz] 35.55 35.1 34.65 34.2 33.75 33.3 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.85 32.4 31.95 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-72. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.
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Figure 34-73. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 0.32 0.30 Step Size [%] 0.28 0.26 0.24 0.22 0.20 0.16 -40°C 105°C 85°C 0.14 25°C 0.18 0.12 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 34.1.9.5 32MHz internal oscillator calibrated to 48MHz Figure 34-74. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55.3 54.6 53.9 Frequency [MHz] 53.2 52.5 51.8 51.1 50.4 49.7 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49.0 48.3 47.6 46.9 46.
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Figure 34-75. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.24 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 48.15 Frequency [MHz] 48.06 47.97 47.88 47.79 47.70 47.61 47.52 47.43 47.34 47.25 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-76. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.29 0.27 Step Size [%] 0.25 0.23 0.21 0.19 -40°C 0.17 25°C 105°C 0.15 0.13 85°C 0.11 0.
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34.1.10 Two-Wire Interface characteristics Figure 34-77. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 34-78. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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34.1.11 PDI characteristics Figure 34-79. Maximum PDI frequency vs. VCC. 22 21 -40°C Frequency max [MHz] 20 19 25°C 18 85°C 105°C 17 16 15 14 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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34.2 ATxmega32C4 34.2.1 Current consumption 34.2.1.1 Active mode supply current Figure 34-80. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 600 550 3.6V 500 ICC [µA] 450 400 3.0V 350 2.7V 300 250 2.2V 200 1.8V 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 34-81. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.6V 9 ICC [mA] 8 3.0V 7 2.7V 6 5 4 2.2V 3 2 1.
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Figure 34-82. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 180 160 -40°C Icc [µA] 140 25°C 85°C 105°C 120 100 80 60 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-83. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 600 -40°C 25°C 85°C 105°C 550 500 Icc [µA] 450 400 350 300 250 200 150 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-84. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1350 1200 -40°C 25 °C 85°C 105°C 1050 Icc [µA] 900 750 600 450 300 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-85. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.0 -40°C 25 °C 85°C 105°C 4.5 4.0 Icc [mA] 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-86. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 -40 °C 11.5 11.0 25 °C 10.5 85 °C 105°C 10.0 Icc [mA] 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 34.2.1.2 Idle mode supply current Figure 34-87. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 120 3.6V 105 90 3.0V ICC[uA] 75 2.7V 60 2.2V 45 1.8V 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 34-88. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.6 3.6V 3.2 Icc [mA] 2.8 3.0V 2.4 2.7V 2.0 1.6 1.2 2.2V 0.8 1.8V 0.4 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frenquecy [MHz] Figure 34-89. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35.50 105°C 34.75 34.00 33.25 32.50 Icc [µA] 31.75 85°C 31.00 -40°C 30.25 25 °C 29.50 28.75 28.00 27.25 26.50 25.75 25.00 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 34-90. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 130 105°C 85 °C 25 °C -40°C 120 110 100 Icc [µA] 90 80 70 60 50 40 30 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-91. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 330 -40°C 25°C 85 °C 105 °C 310 290 270 Icc [µA] 250 230 210 190 170 150 130 110 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-92. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1600 -40 °C 25 °C 85°C 105°C 1500 1400 1300 Icc [µA] 1200 1100 1000 900 800 700 600 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-93. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 4.25 -40°C 4.00 25 °C 85°C 105°C 3.75 Icc [mA] 3.50 3.25 3.00 2.75 2.50 2.25 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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34.2.1.3 Power-down mode supply current Figure 34-94. Power-down mode supply current vs. VCC. All functions disabled. 5.5 105°C 5.0 4.5 4.0 Icc [µA] 3.5 3.0 2.5 2.0 85°C 1.5 1.0 0.5 25°C -40°C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-95. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 6.5 105°C 6.0 5.5 5.0 Icc [µA] 4.5 4.0 3.5 85°C 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-96. Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7.5 7.0 3.6V 6.5 3.0V 2.7V 2.2V 1.8V 6.0 5.5 Icc [µA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 34.2.1.4 Power-save mode supply current Figure 34-97.Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.
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34.2.1.5 Standby mode supply current Figure 34-98. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.1 105°C 10.9 9.7 85°C I CC [µA] 8.5 25°C -40°C 7.3 6.1 4.9 3.7 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-99. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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34.2.2 I/O Pin Characteristics 34.2.2.1 Pull-up Figure 34-100. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 IPIN [µA] 48 40 32 24 -40°C 25°C 85°C 105°C 16 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 34-101. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 -40°C 25°C 85°C 105°C 24 12 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.
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Figure 34-102. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 VPIN [V] 34.2.2.2 Output Voltage vs. Sink/Source Current Figure 34-103. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 85°C 105°C 25°C -40°C 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.
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Figure 34-104. I/O pin output voltage vs. source current. VCC = 3.0V. 3.15 2.80 2.45 VPIN [V] 2.10 1.75 1.40 1.05 25°C -40°C 85°C 105°C 0.70 0.35 0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 34-105. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.15 2.8 VPIN [V] 2.45 2.1 1.75 1.4 1.05 0.7 25°C -40°C 85°C 105°C 0.
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Figure 34-106. I/O pin output voltage vs. source current. 4 VPIN [V] 3.65 3.3 3.6V 3.3V 2.95 3.0V 2.7V 2.6 2.25 1.9 1.8V 1.6V 1.55 1.2 0.85 0.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 34-107. I/O pin output voltage vs. sink current. VCC = 1.8V. 1 0.9 0.8 105°C VPIN [V] 0.7 25°C 85°C -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 34-108. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.1 105°C 85°C 1.0 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 34-109. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1 0.9 105°C 85°C 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 34-110. I/O pin output voltage vs. sink current. 1.5 1.8V 1.6V 1.35 2.7V 3.0V 3.3V 3.6V 1.2 VPIN [V] 1.05 0.9 0.75 0.6 0.45 0.3 0.15 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 34.2.2.3 Thresholds and Hysteresis Figure 34-111. I/O pin input threshold voltage vs. VCC. T = 25C. 1.8 VIH Vthreshold [V] 1.7 1.6 VIL 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-112. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85 °C 105 °C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-113. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40°C 25°C 85 °C 105 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-114. I/O pin input hysteresis vs. VCC. 0.42 0.39 -40°C Vthreshold [V] 0.36 0.33 0.3 25°C 0.27 0.24 85°C 0.21 105°C 0.18 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 34.2.3 ADC Characteristics Figure 34-115. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 34-116. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 34-117. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 34-118. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 34-119. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.
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Figure 34-120. DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 34-121. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 300ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 34-122. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-123. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 34-124. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 0 -2 Gain error [mV] Single-ended signed mode -4 -6 Differential mode -8 -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-125. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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34.2.4 Analog Comparator Characteristics Figure 34-126. Analog comparator hysteresis vs. VCC. High speed, small hysteresis. VHYST [mV] 14 13 105°C 12 85°C 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-127. Analog comparator hysteresis vs. VCC. High speed, large hysteresis. 32 105°C 85°C 30 VHYST [mV] 28 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 34-128. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 30 28 105°C 85°C VHYST [mV] 26 24 25°C 22 -40°C 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-129. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 68 64 105°C 85°C 60 VHYST [mV] 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 34-130. Analog comparator current source vs. calibration value. T = 25C. 8 ICURRENTSOURCE [µA] 7.25 6.5 5.75 5 3.6V 4.25 3.0V 3.5 2.2V 2.75 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..0] Figure 34-131. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.6 ICURRENTSOURCE [µA] 6.2 5.8 5.4 5.0 4.6 4.2 -40°C 25°C 85°C 105°C 3.8 3.4 3.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..
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Figure 34-132. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 34.2.5 Internal 1.0V reference Characteristics Bandgap Voltage [V] Figure 34-133. ADC Internal 1.0V reference vs. temperature. 1.0088 1.008 1.0072 1.0064 1.0056 1.0048 1.004 1.0032 1.0024 1.0016 1.0008 1 0.9992 0.9984 0.9976 0.9968 1.8V 2.2V 2.7V 3.0V 3.
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34.2.6 BOD Characteristics Figure 34-134. BOD thresholds vs. temperature. BOD level = 1.6V. 1.574 Rising Vcc 1.57 Falling Vcc 1.566 VBOT [V] 1.562 1.558 1.554 1.55 1.546 1.542 1.538 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 95 105 Temperature [°C] Figure 34-135. BOD thresholds vs. temperature. BOD level = 3.0V. 2.992 2.984 Rising Vcc 2.976 VBOT [V] 2.968 2.96 2.952 2.944 Falling Vcc 2.936 2.928 2.
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34.2.7 External Reset Characteristics Figure 34-136. Minimum Reset pin pulse width vs. VCC. 145 140 135 130 TRST [ns] 125 120 115 110 105 105°C 85°C 100 95 25°C -40°C 90 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 34-137. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 72 64 IRESET [µA] 56 48 40 32 24 16 -40°C 25°C 85°C 105°C 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 34-138. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 34-139. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 34-140. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. -40°C 25°C 85°C 105°C 2.10 2.00 1.90 1.80 V threshold [V] 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 34-141. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.7 -40°C 25°C 85 °C 105 °C 1.6 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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34.2.8 Power-on Reset Characteristics I CC [µA] Figure 34-142. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 500 85°C 105°C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 34-143. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40°C 585 520 25°C 85°C 105°C I CC [µA] 455 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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34.2.9 Oscillator Characteristics 34.2.9.1 Ultra Low-Power internal oscillator Frequency [kHz] Figure 34-144. Ultra Low-Power internal oscillator frequency vs. temperature. 35.4 35.1 34.8 34.5 34.2 33.9 33.6 33.3 33.0 32.7 32.4 32.1 31.8 31.5 31.2 30.9 3.6V 3.3V 3.0V 2.7V 2.0V 1.8V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 34.2.9.2 32.768kHz Internal Oscillator Figure 34-145. 32.768kHz internal oscillator frequency vs. temperature. 32.9 3.6V 3.3V 3.0V 2.7V 2.
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Figure 34-146. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 51 3.0V Frequency [kHz] 47 43 39 35 31 27 23 19 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL [7..0] 34.2.9.3 2MHz Internal Oscillator Figure 34-147. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 1.96 1.
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Figure 34-148. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.012 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.008 Frequency [MHz] 2.004 2.00 1.996 1.992 1.988 1.984 1.98 1.976 1.972 1.968 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Step Size [%] Figure 34-149. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.
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34.2.9.4 32MHz Internal Oscillator Figure 34-150. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.45 36 Frequency [MHz] 35.55 35.1 34.65 34.2 33.75 33.3 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.85 32.4 31.95 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-151. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.
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Figure 34-152. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 0.32 0.30 Step Size [%] 0.28 0.26 0.24 0.22 0.20 0.16 -40°C 105°C 85°C 0.14 25°C 0.18 0.12 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 34.2.9.5 32MHz internal oscillator calibrated to 48MHz Figure 34-153. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55.3 54.6 53.9 Frequency [MHz] 53.2 52.5 51.8 51.1 50.4 49.7 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49.0 48.3 47.6 46.9 46.
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Figure 34-154. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.24 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 48.15 Frequency [MHz] 48.06 47.97 47.88 47.79 47.70 47.61 47.52 47.43 47.34 47.25 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 34-155. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.29 0.27 Step Size [%] 0.25 0.23 0.21 0.19 -40°C 0.17 25°C 105°C 0.15 0.13 85°C 0.11 0.
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34.2.10 Two-Wire Interface characteristics Figure 34-156. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 34-157. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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34.2.11 PDI characteristics Figure 34-158. Maximum PDI frequency vs. VCC. 22 21 -40°C Frequency max [MHz] 20 19 25°C 18 85°C 105°C 17 16 15 14 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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35. Errata 35.1 ATxmega32C4 35.1.1 Rev. H  AC system status flags are only valid if AC-system is enabled  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
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36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 8493G – 01/2014 1. 36.2 36.3 8493F – 10/2013 1. Updated pin locations of TOSC1 and TOSC2 in Port E - Alternate functions in Table 29-5 on page 53. 2. Updated pin locations of XTAL1, XTAL2, TOSC1 and TOSC2 in Port R - Alternate functions in Table 29-6 on page 53: 8493E – 10/2013 1. 36.
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9. Updated “External clock characteristics” on page 76 and “ External clock characteristics” on page 95. Added Table 33-24 on page 76, Table 33-25 on page 77, Table 33-53 on page 95, and Table 33-54 on page 96. 10. Updated Table 33-26 on page 77, and Table 33-55 on page 96. Added ESR parameter. 11. Updated Table 33-29 on page 82 and Table 33-58 on page 101. Input low voltage VIL min for I2C is -0.5V. 12. Added “Electrical Characteristics” for “ATxmega16C4” on page 64. 13.
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.1 11.2 11.3 11.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . .
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23. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 43 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . .
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36.5 36.6 36.7 8493C – 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8493B – 05/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 8493A – 02/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.