Datasheet
Table Of Contents
- Features
- 1. Ordering Information
- 2. Pinout/Block Diagram
- 3. Overview
- 4. Resources
- 5. Capacitive touch sensing
- 6. AVR CPU
- 7. Memories
- 8. Event System
- 9. System Clock and Clock options
- 9.1 Features
- 9.2 Overview
- 9.3 Clock Sources
- 9.3.1 32kHz Ultra Low Power Internal Oscillator
- 9.3.2 32.768kHz Calibrated Internal Oscillator
- 9.3.3 32.768kHz Crystal Oscillator
- 9.3.4 0.4 - 16MHz Crystal Oscillator
- 9.3.5 2MHz Run-time Calibrated Internal Oscillator
- 9.3.6 32MHz Run-time Calibrated Internal Oscillator
- 9.3.7 External Clock Sources
- 9.3.8 PLL with 1x-31x Multiplication Factor
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. WDT – Watchdog Timer
- 13. Interrupts and Programmable Multilevel Interrupt Controller
- 14. I/O Ports
- 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
- 16. TC2 – Timer/Counter Type 2
- 17. AWeX – Advanced Waveform Extension
- 18. Hi-Res – High Resolution Extension
- 19. RTC – 16-bit Real-Time Counter
- 20. USB – Universal Serial Bus Interface
- 21. TWI – Two-Wire Interface
- 22. SPI – Serial Peripheral Interface
- 23. USART
- 24. IRCOM – IR Communication Module
- 25. CRC – Cyclic Redundancy Check Generator
- 26. ADC – 12-bit Analog to Digital Converter
- 27. AC – Analog Comparator
- 28. Programming and Debugging
- 29. Pinout and Pin Functions
- 30. Peripheral Module Address Map
- 31. Instruction Set Summary
- 32. Packaging information
- 33. Electrical Characteristics TBD
- 34. Typical Characteristics TBD
- 35. Errata
- 36. Datasheet Revision History
- Table of Contents
58
8493A–AVR–02/12
XMEGA C4
31. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1
OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1
COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1
SER Rd Set Register Rd ← $FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2
DES K Data Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
1/2
Branch instructions
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 2
JMP k Jump PC ← k None 3
RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3
(1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2 / 3
(1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 3
(1)