Datasheet

26
8493A–AVR–02/12
XMEGA C4
13. Interrupts and Programmable Multilevel Interrupt Controller
13.1 Features
• Short and predictable interrupt response time
• Separate interrupt configuration and vector address for each interrupt
• Programmable multilevel interrupt controller
– Interrupt prioritizing according to level and vector address
– Three selectable interrupt levels for all interrupts: low, medium and high
– Selectable, round-robin priority scheme within low-level interrupts
– Non-maskable interrupts for critical functions
• Interrupt vectors optionally placed in the application section or the boot loader section
13.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execu-
tion. Peripherals can have one or more interrupts, and all are individually enabled and
configured. When an interrupt is enabled and configured, it will generate an interrupt request
when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC)
controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowl-
edged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt
handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium,
and high. Interrupts are prioritized according to their level and their interrupt vector address.
Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will inter-
rupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is
decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to
ensure that all interrupts are serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical
functions.
13.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address
for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA C3
devices are shown in Table 13-1. Offset addresses for each interrupt available in the peripheral
are described for each peripheral in the XMEGA C manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word
address.
Table 13-1. Reset and interrupt vectors.
Program address
(base address) Source Interrupt description
0x000 RESET
0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI)
0x004 PORTC_INT_base Port C interrupt base
0x008 PORTR_INT_base Port R interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base