Datasheet

XMEGA C3 [DATASHEET]

8492F–AVR–07/2013

7.8 Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from

SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst

read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and

instruction timing.

7.9 Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A

separate register contains the revision number of the device.

7.10 I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the

I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is

enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers

themselves are protected by the configuration change protection mechanism.

7.11 Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the

flash and byte accessible for the EEPROM.

Table 7-2 on page 14 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and

erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash

access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page

number and the least significant address bits (FWORD) give the word in the page.

Table 7-2. Number of words and pages in the flash.

Table 7-3 on page 15 shows EEPROM memory organization. EEEPROM write and erase operations can be performed

one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM

address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page

number and the least significant address bits (E2BYTE) give the byte in the page.

Devices PC size Flash size Page size FWORD FPAGE Application Boot

bits bytes words Size No of pages Size No of pages

ATxmega32C3 16 32K + 4K 128 Z[7:1] Z[16:8] 32K 128 4K 16

ATxmega64C3 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16

ATxmega128C3 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16

ATxmega192C3 17 192K + 8K 256 Z[8:1] Z[17:9] 192K 384 8K 16

ATxmega256C3 18 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16