Datasheet

119
XMEGA C3 [DATASHEET]
8492F–AVR–07/2013
Table 33-87. Two-wire interface characteristics.
Notes: 1. Required only for f
SCL
> 100kHz.
2. C
b
= Capacitance of one bus line in pF.
3. f
PER
= Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
V
IH
Input high voltage 0.7*V
CC
V
CC
+0.5
V
V
IL
Input low voltage -0.5 0.3*V
CC
V
hys
Hysteresis of Schmitt trigger inputs 0.05V
CC
(1)
V
OL
Output low voltage 3mA, sink current 0 0.4
t
r
Rise time for both SDA and SCL 20+0.1C
b
(1)(2)
300
nst
of
Output fall time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(2)
20+0.1C
b
(1)(2)
250
t
SP
Spikes suppressed by input filter 0 50
I
I
Input current for each I/O Pin 0.1V
CC
< V
I
< 0.9V
CC
-10 10 µA
C
I
Capacitance for each I/O Pin 10 pF
f
SCL
SCL clock frequency f
PER
(3)
>max(10f
SCL
, 250kHz) 0 400 kHz
R
P
Value of pull-up resistor
f
SCL
 100kHz

f
SCL
> 100kHz
t
HD;STA
Hold time (repeated) START condition
f
SCL
 100kHz 4.0
µs
f
SCL
> 100kHz 0.6
t
LOW
Low period of SCL clock
f
SCL
 100kHz 4.7
f
SCL
> 100kHz 1.3
t
HIGH
High period of SCL clock
f
SCL
 100kHz 4.0
f
SCL
> 100kHz 0.6
t
SU;STA
Set-up time for a repeated START
condition
f
SCL
 100kHz 4.7
f
SCL
> 100kHz 0.6
t
HD;DAT
Data hold time
f
SCL
 100kHz 0 3.45
µs
f
SCL
> 100kHz 0 0.9
t
SU;DAT
Data setup time
f
SCL
 100kHz 250
f
SCL
> 100kHz 100
t
SU;STO
Setup time for STOP condition
f
SCL
 100kHz 4.0
f
SCL
> 100kHz 0.6
t
BUF
Bus free time between a STOP and
START condition
f
SCL
 100kHz 4.7
f
SCL
> 100kHz 1.3
V
CC
0.4V–
3mA
--------------------------- -
100ns
C
b
-------------- -
300ns
C
b
-------------- -