Datasheet

393
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/Workaround
None.
22. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or
configure these functions or options will have no effect, and will be as writing to a reserved address location.
 TWIE, the TWI module on PORTE
 TWI SDAHOLD option in the TWI CTRL register is one bit
 CRC generator module
 ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
 ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
 ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
 ADC channel scan and the ADC SCAN register
 ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
 ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
 Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
 Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers