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Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–AVR–

03/2014

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 32K - 384KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 2K - 4KBytes EEPROM

 4K - 16KBytes internal SRAM

 Peripheral features

 Four-channel event system

 Five 16-bit timer/counters

 Four timer/counters with four output compare or input capture channels

 One timer/counter with two output compare or input capture channels

 High resolution extension on two timer/counters

 Advanced waveform extension (AWeX) on one timer/counter

 Three USARTs with IrDA support for one USART

 Two two-wire interfaces with dual address match (I

C and SMBus compatible)

 Two serial peripheral interfaces (SPIs)

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE

802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter

 Two Analog Comparators with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 Atmel QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interface

 PDI (program and debug interface)

 I/O and packages

 50 programmable I/O pins

 64-lead TQFP

 64-pad QFN

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel AVR XMEGA D3 Microcontroller

ATxmega32D3* / ATxmega64D3 / ATxmega128D3 /

ATxmega192D3 / ATxmega256D3 / ATxmega384D3*

*Preliminary

Summary of content (430 pages)

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8/16-bit Atmel AVR XMEGA D3 Microcontroller ATxmega32D3* / ATxmega64D3 / ATxmega128D3 / ATxmega192D3 / ATxmega256D3 / ATxmega384D3* *Preliminary Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories          32K - 384KBytes of in-system self-programmable flash 4K - 8KBytes boot section 2K - 4KBytes EEPROM 4K - 16KBytes internal SRAM Peripheral features  Four-channel event system  Five 16-bit timer/counters  Four timer/cou
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1.
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Typical applications Industrial control Climate control Low power battery applications Factory automation RF and ZigBee® Power tools Building control Motor control HVAC Board control Sensor control Utility metering White goods Optical Medical applications XMEGA D3 [DATASHEET] Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014 3
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2. Pinout/block diagram Figure 2-1. Block diagram and pinout.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block diagram Figure 3-1. XMEGA D3 block diagram. PR[0..1] Programming, debug, Power Ground Digital function Analog function /Oscillators XTAL1 External clock /Crystal pins General Purpose I /O XTAL2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on www.atmel.com/avr. 4.1 Recommended reading  Atmel AVR XMEGA D manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   137 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16- and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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Figure 6-1. Block diagram of the AVR CPU architecture. The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file.
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after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device.
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7. Memories 7.
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device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash program memory (Hexadecimal address).
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The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes. Device 7.3.
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Figure 7-2. Data memory map (hexadecimal address).
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7.7 I/O memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly.
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Table 7-2. Number of words and pages in the flash TBD. Devices PC size Flash size Page size FWORD [bits] [bytes] [words] ATxmega32D3 15 32K + 4K 128 Z[7:1] ATxmega64D3 16 64K + 4K 128 ATxmega128D3 17 128K + 8K ATxmega192D3 17 ATxmega256D3 ATxmega384D3 FPAGE Application Boot Size No. of pages Size No.
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8. Event system 8.
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9. System clock and clock options 9.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators:  32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output   External clock options  0.4MHz - 16MHz crystal oscillator 32.
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Figure 9-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 System Clock Prescalers Brown-out Detector Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32kHz Int. ULP 32.768kHz Int. OSC 32.768kHz TOSC 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 9.3 0.
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9.3.1 32kHz ultra low power internal oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 9.3.2 32.
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10. Power management and sleep modes 10.1 Features  Power management for adjusting power consumption and functions  Five sleep modes  Idle Power down  Power save  Standby  Extended standby   Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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10.3.3 Power-save mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 10.3.4 Standby mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 10.3.
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11. System control and reset 11.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 11.
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11.4 Reset sources 11.4.1 Power-on reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. 11.4.
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12. WDT – Watchdog Timer 12.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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13. Interrupts and programmable multilevel interrupt controller 13.
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Table 13-1. Reset and interrupt vectors.
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14. I/O ports 14.
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14.3 Output driver All port pins (Pn) have programmable output configuration. 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input).
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14.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 14-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 14-6. I/O configuration - Wired-AND with optional pull-up.
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14.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7. Figure 14-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.
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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 15.
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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation.
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16. TC2 – Timer/Counter Type 2 16.
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17. AWeX – Advanced Waveform Extension 17.
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18. Hi-Res – High Resolution Extension 18.1 Features  Increases waveform generator resolution up to 8× (three bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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19. RTC – 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator   Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.
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20. TWI – Two-Wire Interface 20.
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21. SPI – Serial Peripheral Interface 21.1 Features  Two identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 21.
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22. USART 22.
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23. IRCOM – IR Communication Module 23.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2kbps  Selectable pulse modulation scheme  3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled   Built-in filtering  Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2kbps.
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24. CRC – Cyclic Redundancy Check generator 24.1 Features  Cyclic redundancy check (CRC) generation and checking for  Communication data Program or data in flash memory  Data in SRAM and I/O memory space   Integrated with flash memory and CPU   Automatic CRC of the complete or a selectable range of the flash memory CPU can load data to the CRC generator through the I/O interface  CRC polynomial software selectable to   CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.3)  Zero remainder detection 24.
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25. ADC – 12-bit Analog to Digital Converter 25.1 Features  One Analog to Digital Converter (ADC)  12-bit resolution  Up to 300 thousand samples per second   Down to 2.3µs conversion time with 8-bit resolution Down to 3.
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Figure 25-1. ADC overview. ADC0 • • • ADC15 Compare Register ADC Internal signals ADC0 • • • ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding.
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26. AC – Analog Comparator 26.
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Figure 26-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis Enable Voltage Scaler ACnCTRL ACnMUXCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26-2. Figure 26-2. Analog comparator window function.
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27. Programming and debugging 27.
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28. Pinout and pin functions The device pinout is shown in “Pinout/block diagram” on page 4. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 28.1 Alternate pin function description The tables below show the notation for all pin functions available and describe its function. 28.1.
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28.1.
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Table 28-1. Port A - Alternate functions. ADCA POS/ PORT A PIN # INTERRUPT GAINPOS ADCA NEG ADCA GAINNEG ACA POS ACA NEG GND 60 AVCC 61 PA0 62 SYNC ADC0 ADC0 AC0 AC0 PA1 63 SYNC ADC1 ADC1 AC1 AC1 PA2 64 SYNC/ASYNC ADC2 ADC2 AC2 PA3 1 SYNC ADC3 ADC3 AC3 PA4 2 SYNC ADC4 ADC4 AC4 PA5 3 SYNC ADC5 ADC5 AC5 PA6 4 SYNC ADC6 ADC6 AC6 PA7 5 SYNC ADC7 ADC7 ACA OUT REFA AREFA AC3 AC5 AC1OUT AC7 AC0OUT Table 28-2. Port B - Alternate functions.
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PORT C TCC0 (1)(2) TWIC CLOCKOUT (5) PC6 22 SYNC OC0DLS MISO RTCOUT PC7 23 SYNC OC0DHS SCK clkPER GND 24 VCC 25 1. 2. 3. 4. 5. 6. TCC1 SPIC (4) INTERRUPT Notes: AWEXC USARTC0 (3) PIN # EVENTOUT (6) EVOUT Pin mapping of all TC0 can optionally be moved to high nibble of port. If TC0 is configured as TC2 all eight pins can be used for PWM output. Pin mapping of all USART0 can optionally be moved to high nibble of port. Pins MOSI and SCK for all SPI can optionally be swapped.
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Table 28-6. Port F - Alternate functions. PORT F PIN # INTERRUPT TCF0 PF0 46 SYNC OC0A PF1 47 SYNC OC0B PF2 48 SYNC/ASYNC OC0C PF3 49 SYNC OC0D PF4 50 SYNC PF5 51 SYNC PF6 54 SYNC PF7 55 SYNC GND 52 VCC 53 Table 28-7. Port R - Alternate functions.
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29. Peripheral module address map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D3. For complete register description and summary for each peripheral module, refer to the XMEGA D manual. Table 29-1. Peripheral module address map.
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Base address Name Description 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 0x08C0 SPIC 0x08F8 IRCOM 0x0900 TCD0 0x09A0 USARTD0 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A80 AWEXE 0x0AA0 USAR
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30.
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Mnemonics Operands Description Operation Flags #Clocks PC(15:0) PC(21:16)   Z, EIND None 3 (1) call Subroutine PC  k None 3 / 4 (1) RET Subroutine Return PC  STACK None 4 / 5 (1) RETI Interrupt Return PC  STACK I 4 / 5 (1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 EICALL CALL Extended Indirect Call to (Z) k CPSE Rd, Rr Compare, Skip if Equal CP Rd, Rr Compare CPC Rd, Rr Compare with Carry CPI Rd, K Compare with Immediate SBRC Rr, b Skip if Bit in Reg
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Mnemonics Operands Description Flags #Clocks LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y+1 None 1 (1)(2) LD Rd, -Y Load Indirect and Pre-Decrement Y Rd   Y-1 (Y) None 2 (1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd  (Y + q)
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Mnemonics Operands Description PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Operation Flags #Clocks STACK  Rr None 1 (1) Rd  STACK None 2 (1) Rd(n+1) Rd(0) C    Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C    Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C    C, Rd(n), Rd(7) Z,C,N,V,H 1 Bit and bit-test instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry Rd(7
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Mnemonics Operands Description Operation Flags #Clocks None 1 NOP No Operation SLEEP Sleep (See specific descr. for Sleep) None 1 Watchdog Reset (See specific descr. for WDR) None 1 WDR Notes: 1. 2. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing internal SRAM.
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31. Packaging information 31.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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31.
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32. Electrical characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 32.1 Atmel ATxmega32D3 32.1.1 Absolute maximum ratings Stresses beyond those listed in Table 32-30 on page 82 under may cause permanent damage to the device.
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Table 32-3. Operating voltage and frequency. Symbol Parameter ClkCPU CPU clock frequency Condition Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 32-1. Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
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32.1.3 Current consumption Table 32-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 50 VCC = 3.0V 130 VCC = 1.8V 215 VCC = 3.0V 475 VCC = 1.8V 445 600 0.95 1.5 7.8 12.0 Power-down power consumption VCC = 3.0V 3 VCC = 1.8V 46 VCC = 3.0V 92 VCC = 1.8V 93 225 184 350 2.9 5.0 0.
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Table 32-5. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Typ. ULP oscillator 0.9 32.768kHz int. oscillator 29 Max. Units 82 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 114 250 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 400 20× multiplication factor, 32MHz int. osc. DIV4 as reference 300 Watchdog timer µA 1.0 Continuous mode 140 Sampled mode, includes ULP oscillator 1.
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32.1.4 Wake-up time from sleep modes Table 32-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 125 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.6 32.768kHz internal oscillator 330 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Max.
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32.1.5 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-7. I/O pin characteristics. Symbol IOH (1) / IOL High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor 1. 2. Condition Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.
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32.1.6 ADC characteristics Table 32-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 1 AVCC - 0.6 Units V Rin Input resistance Switched 4.
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Table 32-10. Accuracy characteristics. Symbol RES Condition (2) Parameter Resolution 12-bit resolution Differential mode INL (1) Integral non-linearity Single ended unsigned mode Differential mode DNL (1) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: 1. 2. Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
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Table 32-11. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Max. Units Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 0 1 0.5× gain, normal mode -1 1× gain, normal mode -1 8× gain, normal mode -1 64× gain, normal mode 5 0.
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32.1.8 Bandgap and internal 1.0V reference characteristics Table 32-13. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1 1.01 1 % 32.1.9 Brownout detection characteristics Table 32-14.
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32.1.11 Power-on reset characteristics Table 32-16. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.1.12 Flash and EEPROM memory characteristics Table 32-17.
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32.1.13 Clock and oscillator characteristics 32.1.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-19. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.1.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-20. 2MHz internal oscillator characteristics.
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32.1.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-23. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
PAGE 76
Table 32-25. External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
PAGE 77
Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
PAGE 78
Symbol Parameter CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Note: 1. Condition Min. Typ. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.1.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-27. External 32.768kHz crystal oscillator and TOSC characteristics.
PAGE 79
32.1.14 SPI characteristics Figure 32-5. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-6. SPI timing requirements in slave mode.
PAGE 80
Table 32-28. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
PAGE 81
Table 32-29. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC + 0.5 VIL Input low voltage -0.5 0.
PAGE 82
32.2 Atmel ATxmega64D3 32.2.1 Absolute maximum ratings Stresses beyond those listed in Table 32-30 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-30. Absolute maximum ratings. Symbol Parameter Condition Min.
PAGE 83
Figure 32-8. Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
PAGE 84
32.2.3 Current consumption Table 32-33. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 50 VCC = 3.0V 130 VCC = 1.8V 215 VCC = 3.0V 475 VCC = 1.8V 445 600 0.95 1.5 7.8 12.0 Power-down power consumption VCC = 3.0V 3 VCC = 1.8V 46 VCC = 3.0V 92 VCC = 1.8V 93 225 184 350 2.9 5.0 0.
PAGE 85
Table 32-34. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Typ. ULP oscillator 0.9 32.768kHz int. oscillator 29 Max. Units 82 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 114 250 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 400 20× multiplication factor, 32MHz int. osc. DIV4 as reference 300 Watchdog timer µA 1.0 Continuous mode 140 Sampled mode, includes ULP oscillator 1.
PAGE 86
32.2.4 Wake-up time from sleep modes Table 32-35. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 125 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.6 32.768kHz internal oscillator 330 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Max.
PAGE 87
32.2.5 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-36. I/O pin characteristics. Symbol IOH (1) / IOL High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor 1. 2. Condition Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.
PAGE 88
32.2.6 ADC characteristics Table 32-37. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 1 AVCC - 0.6 Units V Rin Input resistance Switched 4.
PAGE 89
Table 32-39. Accuracy characteristics. Symbol RES Condition (2) Parameter Resolution 12-bit resolution Differential mode INL (1) Integral non-linearity Single ended unsigned mode Differential mode DNL (1) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
PAGE 90
Table 32-40. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Max. Units Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 0 1 0.5× gain, normal mode -1 1× gain, normal mode -1 8× gain, normal mode -1 64× gain, normal mode 5 0.
PAGE 91
32.2.8 Bandgap and internal 1.0V reference characteristics Table 32-42. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1 1.01 1 % 32.2.9 Brownout detection characteristics Table 32-43.
PAGE 92
32.2.11 Power-on reset characteristics Table 32-45. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.2.12 Flash and EEPROM memory characteristics Table 32-46.
PAGE 93
32.2.13 Clock and oscillator characteristics 32.2.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-48. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.2.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-49. 2MHz internal oscillator characteristics.
PAGE 94
32.2.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-52. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
PAGE 95
Table 32-54. External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
PAGE 96
Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
PAGE 97
Symbol Parameter CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Note: 1. Condition Min. Typ. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.2.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-56. External 32.768kHz crystal oscillator and TOSC characteristics.
PAGE 98
32.2.14 SPI characteristics Figure 32-12. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-13.SPI timing requirements in slave mode.
PAGE 99
Table 32-57. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
PAGE 100
Table 32-58. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC + 0.5 VIL Input low voltage -0.5 0.
PAGE 101
32.3 Atmel ATxmega128D3 32.3.1 Absolute maximum ratings Stresses beyond those listed in Table 32-59 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-59. Absolute maximum ratings. Symbol Parameter Condition Min.
PAGE 102
Figure 32-15.Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
PAGE 103
32.3.3 Current consumption Table 32-62. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 55 VCC = 3.0V 135 VCC = 1.8V 237 VCC = 3.0V 515 VCC = 1.8V 425 700 0.9 1.5 8.3 12 Power-down power consumption VCC = 3.0V 3.1 VCC = 1.8V 47 VCC = 3.0V 95 VCC = 1.8V 94 200 190 400 3.0 7.0 0.1 1.
PAGE 104
Table 32-63. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Typ. ULP oscillator 0.9 32.768kHz int. oscillator 26 Max. Units 79 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 245 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 415 20× multiplication factor, 32MHz int. osc. DIV4 as reference 305 Watchdog timer µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
PAGE 105
32.3.4 Wake-up time from sleep modes Table 32-64. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 130 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max.
PAGE 106
32.3.5 I/O pin characteristics The I/O pins compiles with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits or exceeds this specification. Table 32-65. I/O pin characteristics. Symbol IOH (1) / IOL High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor 1. 2. Condition Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.
PAGE 107
32.3.6 ADC characteristics Table 32-66. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 1 AVCC - 0.6 Units V Rin Input resistance Switched 4.
PAGE 108
Table 32-68. Accuracy characteristics. Symbol RES Condition (2) Parameter Resolution 12-bit resolution Differential mode INL (1) Integral non-linearity Single ended unsigned mode Differential mode DNL (1) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: 1. 2. Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
PAGE 109
Table 32-69. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 0.
PAGE 110
32.3.8 Bandgap and internal 1.0V reference characteristics Table 32-71. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1.0 1.01 1 % 32.3.9 Brownout detection characteristics Table 32-72.
PAGE 111
32.3.11 Power-on reset characteristics Table 32-74. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.3.12 Flash and EEPROM memory characteristics Table 32-75.
PAGE 112
32.3.13 Clock and oscillator characteristics 32.3.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-77. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.3.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-78. 2MHz internal oscillator characteristics.
PAGE 113
32.3.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-81. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
PAGE 114
Table 32-83. External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
PAGE 115
Symbol Parameter Condition 44k 1MHz resonator, CL=20pF 67k 2MHz resonator, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal
PAGE 116
Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL1 pin 8.3 CLOAD Parasitic capacitance load 3.5 Note: 1. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.3.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-85. External 32.768kHz crystal oscillator and TOSC characteristics.
PAGE 117
32.3.14 SPI characteristics Figure 32-19.SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-20.SPI timing requirements in slave mode.
PAGE 118
Table 32-86. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
PAGE 119
Table 32-87. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC + 0.5 VIL Input low voltage -0.5 0.
PAGE 120
32.4 Atmel ATxmega192D3 32.4.1 Absolute maximum ratings Stresses beyond those listed in Table 32-88 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-88. Absolute maximum ratings. Symbol Parameter Condition Min.
PAGE 121
Figure 32-22.Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
PAGE 122
32.4.3 Current consumption Table 32-91. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (2) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 60 VCC = 3.0V 140 VCC = 1.8V 245 VCC = 3.0V 550 VCC = 1.8V 440 700 0.9 1.5 9.0 15 Power-down power consumption VCC = 3.0V 3.5 VCC = 1.8V 55 VCC = 3.0V 110 VCC = 1.8V 105 350 215 650 3.4 8.0 0.
PAGE 123
Table 32-92. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Typ. ULP oscillator 0.9 32.768kHz int. oscillator 25 Max. Units 78 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 250 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 440 20× multiplication factor, 32MHz int. osc. DIV4 as reference 310 Watchdog timer µA 1.0 Continuous mode 132 Sampled mode, includes ULP oscillator 1.
PAGE 124
32.4.4 Wake-up time from sleep modes Table 32-93. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 125 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.6 32.768kHz internal oscillator 330 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Max.
PAGE 125
32.4.5 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-94. I/O pin characteristics. Symbol IOH (1) / IOL High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor 1. 2. Condition Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.
PAGE 126
32.4.6 ADC characteristics Table 32-95. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 1 AVCC - 0.6 Units V Rin Input resistance Switched 4.
PAGE 127
Table 32-97. Accuracy characteristics. Symbol RES Condition (2) Parameter Resolution 12-bit resolution Differential mode INL (1) Integral non-linearity Single ended unsigned mode Differential mode DNL (1) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: 1. 2. Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
PAGE 128
Table 32-98. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 0 1 0.5× gain, normal mode -1 1× gain, normal mode -1 8× gain, normal mode -1 64× gain, normal mode 5 0.
PAGE 129
32.4.8 Bandgap and internal 1.0V reference characteristics Table 32-100. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1.0 1.01 1 % 32.4.9 Brownout detection characteristics Table 32-101.
PAGE 130
32.4.11 Power-on reset characteristics Table 32-103.Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.4.12 Flash and EEPROM memory characteristics Table 32-104.
PAGE 131
32.4.13 Clock and oscillator characteristics 32.4.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-106. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.4.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-107. 2MHz internal oscillator characteristics.
PAGE 132
32.4.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-110. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
PAGE 133
Table 32-112.External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
PAGE 134
Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
PAGE 135
Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Notes: 1. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.4.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-114. External 32.768kHz crystal oscillator and TOSC characteristics.
PAGE 136
32.4.14 SPI characteristics Figure 32-26. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-27. SPI timing requirements in slave mode.
PAGE 137
Table 32-115. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
PAGE 138
Table 32-116. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC + 0.5 VIL Input low voltage -0.5 0.
PAGE 139
32.5 Atmel ATxmega256D3 32.5.1 Absolute maximum ratings Stresses beyond those listed in Table 32-117 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-117. Absolute maximum ratings. Symbol Parameter Condition Min.
PAGE 140
Figure 32-29. Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
PAGE 141
32.5.3 Current consumption Table 32-120. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (2) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 60 VCC = 3.0V 140 VCC = 1.8V 245 VCC = 3.0V 550 VCC = 1.8V 440 700 0.9 1.5 9.0 15 Power-down power consumption VCC = 3.0V 3.5 VCC = 1.8V 55 VCC = 3.0V 110 VCC = 1.8V 105 350 215 650 3.4 8.0 0.
PAGE 142
Table 32-121. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Typ. ULP oscillator 0.9 32.768kHz int. oscillator 25 Max. Units 78 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 250 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 440 20× multiplication factor, 32MHz int. osc. DIV4 as reference 310 Watchdog timer µA 1.0 Continuous mode 132 Sampled mode, includes ULP oscillator 1.
PAGE 143
32.5.4 Wake-up time from sleep modes Table 32-122. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 125 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.6 32.768kHz internal oscillator 330 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Max.
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32.5.5 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-123. I/O pin characteristics. Symbol IOH (1) / IOL High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor 1. 2. Condition Max. Units -15 15 mA VCC = 2.4 - 3.6V 0.
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32.5.6 ADC characteristics Table 32-124. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC - 0.3 VCC + 0.3 1 AVCC - 0.6 Units V Rin Input resistance Switched 4.
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Table 32-126. Accuracy characteristics. Symbol RES Condition (2) Parameter Resolution 12-bit resolution Differential mode INL (1) Integral non-linearity Single ended unsigned mode Differential mode DNL (1) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: 1. 2. Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
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Table 32-127. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 0 1 0.5× gain, normal mode -1 1× gain, normal mode -1 8× gain, normal mode -1 64× gain, normal mode 5 0.
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32.5.8 Bandgap and internal 1.0V reference characteristics Table 32-129. Symbol Bandgap and internal 1.0V reference characteristics. Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1.0 1.01 1 % 32.5.9 Brownout detection characteristics Table 32-130.
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32.5.11 Power-on reset characteristics Table 32-132. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. 32.5.12 Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. Flash and EEPROM memory characteristics Table 32-133.
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32.5.13 Clock and oscillator characteristics 32.5.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-135. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.5.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-136. 2MHz internal oscillator characteristics.
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32.5.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-139. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
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Table 32-141.External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
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Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
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Symbol Parameter Condition Min. Typ. CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Notes: 1. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.5.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-143. External 32.768kHz crystal oscillator and TOSC characteristics.
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32.5.14 SPI characteristics Figure 32-33. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 32-34. SPI timing requirements in slave mode.
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Table 32-144. SPI timing characteristics and requirements. Symbol Parameter Condition tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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Table 32-145. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC + 0.5 VIL Input low voltage -0.5 0.
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32.6 Atmel ATxmega384D3 32.6.1 Absolute maximum ratings Stresses beyond those listed in Table 32-146 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-146. Absolute maximum ratings. Symbol Parameter Condition Min.
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Figure 32-36. Maximum frequency vs. VCC. MHz 32 Safe operating area 12 1.6 1.8 2.7 3.
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32.6.3 Current consumption Table 32-149. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 150 VCC = 3.0V 320 VCC = 1.8V 410 VCC = 3.0V 830 VCC = 1.8V 660 800 1.3 1.8 10 15 Power-down power consumption VCC = 3.0V 5 VCC = 1.8V 50 VCC = 3.0V 100 VCC = 1.8V 100 350 200 600 3.3 7 0.2 1.
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Table 32-150. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. ULP oscillator Typ. Max. Units 0.93 32.768kHz int. oscillator 27 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 240 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 430 20× multiplication factor, 32MHz int. osc. DIV4 as reference 300 µA PLL Watchdog timer 1 Continuous mode 140 Sampled mode, includes ULP oscillator 1.
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32.6.4 Wake-up time from sleep modes Table 32-151. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 130 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max.
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32.6.5 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-152. I/O pin characteristics. Symbol Parameter IOH (1)/ IOL (2) High level input voltage VIL Low level input voltage VOL High level output voltage Low level output voltage IIN Input leakage current I/O pin RP Pull/buss keeper resistor Notes: 1. 2. Max. Units -15 15 mA VCC = 2.4 - 3.
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Symbol Parameter Vin Input range V Condition Min. Conversion range Differential mode, Vinp - Vinn Conversion range Single ended unsigned mode, Vinp Typ. Max. 0 VREF -VREF VREF -V VREF - V Fixed offset voltage 200 Units V lsb Table 32-154. Clock and timing. Symbol Parameter ClkADC ADC clock frequency fClkADC Sample rate fADC Condition Min. Typ. Max.
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Table 32-155. Accuracy characteristics. Symbol RES Condition (1) Parameter Resolution 12-bit resolution Differential mode INL (2) Integral non-linearity Single ended unsigned mode Differential mode DNL (2) Differential non-linearity Single ended unsigned mode Offset error Gain error Gain error Notes: 1. 2. Differential mode Differential mode Single ended unsigned mode Min. Typ. Max.
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Table 32-156. Gain stage characteristics. Symbol Rin Csample Parameter Condition Min. Typ. Input resistance Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock rate Same as ADC 100 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 5 0.
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32.6.8 Bandgap and internal 1.0V reference characteristics Table 32-158. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min. As reference for ADC Typ. Max. 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration Variation over voltage and temperature Calibrated at T = 85°C 0.99 1 1.01 2 % 32.6.9 Brownout detection characteristics Table 32-159.
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32.6.11 Power-on reset characteristics Table 32-161. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. 32.6.12 Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.3 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. Flash and EEPROM memory characteristics Table 32-162.
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32.6.13 Clock and oscillator characteristics 32.6.13.1 Calibrated 32.768kHz internal oscillator characteristics Table 32-164. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.6.13.2 Calibrated 2MHz RC internal oscillator characteristics Table 32-165. 2MHz internal oscillator characteristics. Symbol Parameter Condition Min.
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32.6.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-168. Internal PLL characteristics. Symbol fIN Parameter Condition Input frequency Output frequency must be within fOUT 0.4 64 VCC = 1.6 - 1.8V 20 48 VCC = 2.7 - 3.6V 20 128 Output frequency (1) fOUT Min. Typ. Start-up time 25 Re-lock time 25 Max. Units MHz µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
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Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. Table 32-170.External clock with prescaler (1) for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.
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Symbol Parameter Condition XOSCPWR=0 Min. Typ. FRQRANGE=0 50 FRQRANGE=1 50 FRQRANGE=2 or 3 50 Max.
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Symbol Parameter Start-up time Condition Min. Typ. XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0 XOSCPWR=0, FRQRANGE=1 2MHz crystal, CL=20pF 2.6 XOSCPWR=0, FRQRANGE=2 8MHz crystal, CL=20pF 0.8 XOSCPWR=0, FRQRANGE=3 12MHz crystal, CL=20pF 1.0 XOSCPWR=1, FRQRANGE=3 16MHz crystal, CL=20pF 1.4 CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 Parasitic capacitance load 3.5 CLOAD Note: 1. Max.
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Figure 32-39. TOSC input capacitance. CL1 CL2 Device internal External TOSC1 TOSC2 32.768 kHz crystal The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 32.6.14 SPI characteristics Figure 32-40. SPI timing requirements in master mode.
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Figure 32-41. SPI timing requirements in slave mode. SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data input) tSIH MSB tSOSSS MISO (Data output) tSSCK LSB tSOS tSOSSH MSB LSB Table 32-173. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA D manual) tSCKW SCK high/low width Master 0.5 * SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.
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32.6.15 Two-wire interface characteristics Table 32-174 on page 176 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-42. Figure 32-42. Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 32-174. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.3 Units µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency.
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33. Typical characteristics 33.1 Atmel ATxmega32D3 33.1.1 Active supply current Figure 33-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 900 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 33-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. ICC [mA] 20 18 3.3V 16 3.0V 14 2.7V 12 10 8 2.2V 6 4 1.
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Figure 33-3. Active supply current vs. VCC. fSYS = 1.0MHz external clock. 85°C 25°C -40°C 1000 900 800 ICC [µA] 700 600 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-4. Active supply current vs. VCC. fSYS = 32.768kHz internal RC. 140 -40°C 25°C 85°C 120 ICC [µA] 100 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-5. Active supply current vs. VCC. fSYS = 2.0MHz internal RC. 2000 -40°C 25°C 85°C 1800 1600 ICC [µA] 1400 1200 1000 800 600 400 200 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-6. Active supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 8 -40°C 25°C 85°C 7 6 ICC [mA] 5 4 3 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-7. Active supply current vs. VCC. fSYS = 32MHz internal RC. 25 -40°C 25°C 85°C ICC [mA] 20 15 10 5 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.1.2 Idle supply current Figure 33-8. Idle supply current vs. frequency. fSYS = 0 - 1.0MHz, T = 25°C. 250 3.3V 3.0V 200 ICC [µA] 2.7V 150 2.2V 1.8V 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 33-9. Idle supply current vs. frequency. fSYS = 1 - 32MHz, T = 25°C. 8 3.3V 7 3.0V 6 2.7V ICC [mA] 5 4 3 2.2V 2 1.8V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-10. Idle supply current vs. VCC. fSYS = 1.0MHz external clock. 300 85°C 25°C -40°C 250 ICC [µA] 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-11. Idle supply current vs. VCC. fSYS = 32.768kHz internal RC. 40 85°C -40°C 25°C 35 30 ICC [µA] 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-12. Idle supply current vs. VCC. fSYS = 2.0MHz internal RC. 700 -40°C 25°C 85°C 600 ICC [µA] 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-13. Idle supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 3.5 -40°C 25°C 85°C 3.0 ICC [mA] 2.5 2.0 1.5 1.0 0.5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-14. Idle supply current vs. VCC. fSYS = 32MHz internal RC. 10 -40°C 25°C 85°C ICC [mA] 8 6 4 2 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.1.3 Power-down supply current Figure 33-15. Power-down supply current vs. temperature. 2.0 3.3V 3.0V 2.7V 2.2V 1.8V 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 33-16. Power-down supply current vs. temperature. With WDT and sampled BOD enabled. 3.3V 3.0V 2.7V 2.2V 1.8V 3.0 2.5 ICC [µA] 2.0 1.5 1.0 0.
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33.1.4 Power-save supply current Figure 33-17. Power-save supply current vs. temperature. With WDT, sampled BOD, and RTC from ULP enabled. 3.0 3.3V 3.0V 2.7V 1.8V 2.2V 2.5 ICC [µA] 2.0 1.5 1.0 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 33.1.5 Pin pull-up Figure 33-18. Reset pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 33-19. Reset pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 160 140 IRESET [µA] 120 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 33-20. Reset pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 180 160 140 IRESET [µA] 120 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.
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33.1.6 Pin output voltage vs. sink/source current Figure 33-21. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 -40°C 25°C 85°C 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 33-22. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 -40°C 25°C 85°C 3.0 VPIN [V] 2.5 2.0 1.5 1.0 0.
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Figure 33-23. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 -40°C 25°C 85°C 3.0 VPIN [V] 2.5 2.0 1.5 1.0 0.5 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 33-24. I/O pin output voltage vs. sink current. VCC = 1.8V. 85°C 25°C 1.8 1.6 1.4 VPIN [V] 1.2 -40°C 1.0 0.8 0.6 0.4 0.
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Figure 33-25. I/O pin output voltage vs. sink current. VCC = 3.0V. 0.7 85°C 0.6 25°C -40°C VPIN [V] 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IPIN [mA] Figure 33-26. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 0.7 0.6 85°C 0.5 25°C -40°C 0.4 0.3 0.2 0.
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33.1.7 Thresholds and hysteresis Figure 33-27. I/O pin input threshold voltage vs. VCC. VIH - I/O pin read as “1”. 2.5 -40°C 25°C 85°C Vthreshold [V] 2.0 1.5 1.0 0.5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-28. I/O pin input threshold voltage vs. VCC. VIL - I/O pin read as “0”. 1.8 85°C 25°C -40°C 1.6 1.4 Vthreshold [V] 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-29. I/O pin input hysteresis vs. VCC. 0.7 0.6 Vthreshold [V] 0.5 85°C 25°C -40°C 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-30. Reset input threshold voltage vs. VCC. VIL - I/O pin read as “1”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-31. Reset input threshold voltage vs. VCC. VIL - I/O pin read as “0”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.1.8 BOD thresholds Figure 33-32. BOD thresholds vs. temperature. BOD level = 1.6V. VBOT [V] 1.67 1.66 Rising Vcc 1.65 Falling Vcc 1.64 1.63 1.62 1.
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Figure 33-33. BOD thresholds vs. temperature. BOD level = 2.9V. 3.06 3.04 Rising Vcc 3.02 VBOT [V] 3.00 2.98 Falling Vcc 2.96 2.94 2.92 2.90 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 33.1.9 Oscillators and wake-up time Internal 32.768kHz oscillator Figure 33-34. Internal 32.768kHz oscillator calibration step size. T = -40 to 85°C, VCC = 3V. 0.80% 0.65% Step size: f [kHz] 33.1.9.1 0.50% 0.35% 0.20% 0.05% 0 32 64 96 128 160 192 224 256 RC32KCAL[7..
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Internal 2MHz oscillator Figure 33-35. Internal 2MHz oscillator CALA calibration step size. T = -40 to 85°C, VCC = 3V. 0.50% 0.40% Step size: f [MHz] 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% 0 16 32 48 64 80 96 112 128 56 64 DFLLRC2MCALA Figure 33-36. Internal 2MHz oscillator CALB calibration step size. T = -40 to 85°C, VCC = 3V. 3.00% 2.50% Step size: f [MHz] 33.1.9.2 2.00% 1.50% 1.00% 0.50% 0.
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Internal 32MHz oscillator Figure 33-37. Internal 32MHz oscillator CALA calibration step size. T = -40 to 85°C, VCC = 3V. 0.60% 0.50% Step size: f [MHz] 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% 0 16 32 48 64 80 96 112 128 56 64 DFLLRC32MCALA Figure 33-38. Internal 32MHz oscillator CALB calibration step size. T = -40 to 85°C, VCC = 3V. 3.00% 2.50% Step size: f [MHz] 33.1.9.3 2.00% 1.50% 1.00% 0.50% 0.
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Module current consumption Figure 33-39. AC current consumption vs. VCC. Low-power mode. Module current consumption [µA] 120 85°C 25°C 100 -40°C 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-40. Power-up current consumption vs. VCC. -40°C 25°C 85°C 700 600 500 ICC [µA] 33.1.10 400 300 200 100 0 0.4 0.6 0.8 1.0 1.2 1.4 1.
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33.1.11 Reset pulse width Figure 33-41. Minimum reset pulse width vs. VCC. 120 100 85°C 25°C -40°C tRST [ns] 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] PDI speed Figure 33-42. PDI speed vs. VCC. 35 25°C 30 25 fMAX [MHz] 33.1.12 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.2 Atmel ATxmega64D3 33.2.1 Active supply current Figure 33-43. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 900 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 33-44. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. ICC [mA] 20 18 3.3V 16 3.0V 14 2.7V 12 10 8 2.2V 6 4 1.
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Figure 33-45. Active supply current vs. VCC. fSYS = 1.0MHz external clock. 85°C 25°C -40°C 1000 900 800 ICC [µA] 700 600 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-46. Active supply current vs. VCC. fSYS = 32.768kHz internal RC. 140 -40°C 25°C 85°C 120 ICC [µA] 100 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-47. Active supply current vs. VCC. fSYS = 2.0MHz internal RC. 2000 -40°C 25°C 85°C 1800 1600 ICC [µA] 1400 1200 1000 800 600 400 200 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-48. Active supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 8 -40°C 25°C 85°C 7 6 ICC [mA] 5 4 3 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-49. Active supply current vs. VCC. fSYS = 32MHz internal RC. 25 -40°C 25°C 85°C ICC [mA] 20 15 10 5 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.2.2 Idle supply current Figure 33-50. Idle supply current vs. frequency. fSYS = 0 - 1.0MHz, T = 25°C. 250 3.3V 3.0V 200 ICC [µA] 2.7V 150 2.2V 1.8V 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 33-51. Idle supply current vs. frequency. fSYS = 1 - 32MHz, T = 25°C. 8 3.3V 7 3.0V 6 2.7V ICC [mA] 5 4 3 2.2V 2 1.8V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-52. Idle supply current vs. VCC. fSYS = 1.0MHz external clock. 300 85°C 25°C -40°C 250 ICC [µA] 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-53. Idle supply current vs. VCC. fSYS = 32.768kHz internal RC. 40 85°C -40°C 25°C 35 30 ICC [µA] 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-54. Idle supply current vs. VCC. fSYS = 2.0MHz internal RC. 700 -40°C 25°C 85°C 600 ICC [µA] 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-55. Idle supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 3.5 -40°C 25°C 85°C 3.0 ICC [mA] 2.5 2.0 1.5 1.0 0.5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-56. Idle supply current vs. VCC. fSYS = 32MHz internal RC. 10 -40°C 25°C 85°C ICC [mA] 8 6 4 2 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.2.3 Power-down supply current Figure 33-57. Power-down supply current vs. temperature. 2.0 3.3V 3.0V 2.7V 2.2V 1.8V 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 33-58. Power-down supply current vs. temperature. With WDT and sampled BOD enabled. 3.3V 3.0V 2.7V 2.2V 1.8V 3.0 2.5 ICC [µA] 2.0 1.5 1.0 0.
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33.2.4 Power-save supply current Figure 33-59. Power-save supply current vs. temperature. With WDT, sampled BOD, and RTC from ULP enabled. 3.0 3.3V 3.0V 2.7V 1.8V 2.2V 2.5 ICC [µA] 2.0 1.5 1.0 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 33.2.5 Pin pull-up Figure 33-60. Reset pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 33-61. Reset pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 160 140 IRESET [µA] 120 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 33-62. Reset pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 180 160 140 IRESET [µA] 120 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.
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33.2.6 Pin output voltage vs. sink/source current Figure 33-63. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 -40°C 25°C 85°C 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 33-64. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 -40°C 25°C 85°C 3.0 VPIN [V] 2.5 2.0 1.5 1.0 0.
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Figure 33-65. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 -40°C 25°C 85°C 3.0 VPIN [V] 2.5 2.0 1.5 1.0 0.5 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 33-66. I/O pin output voltage vs. sink current. VCC = 1.8V. 85°C 25°C 1.8 1.6 1.4 VPIN [V] 1.2 -40°C 1.0 0.8 0.6 0.4 0.
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Figure 33-67. I/O pin output voltage vs. sink current. VCC = 3.0V. 0.7 85°C 0.6 25°C -40°C VPIN [V] 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IPIN [mA] Figure 33-68. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 0.7 0.6 85°C 0.5 25°C -40°C 0.4 0.3 0.2 0.
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33.2.7 Thresholds and hysteresis Figure 33-69. I/O pin input threshold voltage vs. VCC. VIH - I/O pin read as “1”. 2.5 -40°C 25°C 85°C Vthreshold [V] 2.0 1.5 1.0 0.5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-70. I/O pin input threshold voltage vs. VCC. VIL - I/O pin read as “0”. 1.8 85°C 25°C -40°C 1.6 1.4 Vthreshold [V] 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-71. I/O pin input hysteresis vs. VCC. 0.7 0.6 Vthreshold [V] 0.5 85°C 25°C -40°C 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-72. Reset input threshold voltage vs. VCC. VIL - I/O pin read as “1”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-73. Reset input threshold voltage vs. VCC. VIL - I/O pin read as “0”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.2.8 BOD thresholds Figure 33-74. BOD thresholds vs. temperature. BOD level = 1.6V. VBOT [V] 1.67 1.66 Rising Vcc 1.65 Falling Vcc 1.64 1.63 1.62 1.
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Figure 33-75. BOD thresholds vs. temperature. BOD level = 2.9V. 3.06 3.04 Rising Vcc 3.02 VBOT [V] 3.00 2.98 Falling Vcc 2.96 2.94 2.92 2.90 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 33.2.9 Oscillators and wake-up time Internal 32.768kHz oscillator Figure 33-76. Internal 32.768kHz oscillator calibration step size. T = -40 to 85°C, VCC = 3V. 0.80% 0.65% Step size: f [kHz] 33.2.9.1 0.50% 0.35% 0.20% 0.05% 0 32 64 96 128 160 192 224 256 RC32KCAL[7..
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Internal 2MHz oscillator Figure 33-77. Internal 2MHz oscillator CALA calibration step size. T = -40 to 85°C, VCC = 3V. 0.50% 0.40% Step size: f [MHz] 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% 0 16 32 48 64 80 96 112 128 56 64 DFLLRC2MCALA Figure 33-78. Internal 2MHz oscillator CALB calibration step size. T = -40 to 85°C, VCC = 3V. 3.00% 2.50% Step size: f [MHz] 33.2.9.2 2.00% 1.50% 1.00% 0.50% 0.
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Internal 32MHz oscillator Figure 33-79. Internal 32MHz oscillator CALA calibration step size. T = -40 to 85°C, VCC = 3V. 0.60% 0.50% Step size: f [MHz] 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% 0 16 32 48 64 80 96 112 128 56 64 DFLLRC32MCALA Figure 33-80. Internal 32MHz oscillator CALB calibration step size. T = -40 to 85°C, VCC = 3V. 3.00% 2.50% Step size: f [MHz] 33.2.9.3 2.00% 1.50% 1.00% 0.50% 0.
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Module current consumption Figure 33-81. AC current consumption vs. VCC. Low-power mode. Module current consumption [µA] 120 85°C 25°C 100 -40°C 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-82. Power-up current consumption vs. VCC. -40°C 25°C 85°C 700 600 500 ICC [µA] 33.2.10 400 300 200 100 0 0.4 0.6 0.8 1.0 1.2 1.4 1.
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33.2.11 Reset pulse width Figure 33-83. Minimum reset pulse width vs. VCC. 120 100 85°C 25°C -40°C tRST [ns] 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] PDI speed Figure 33-84. PDI speed vs. VCC. 35 25°C 30 25 fMAX [MHz] 33.2.12 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.3 Atmel ATxmega128D3 33.3.1 Current consumption Active supply current Figure 33-85. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 Icc [µA] 700 3.6V 600 3.3V 500 3.0V 2.7V 400 2.2V 300 1.8V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-86. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 12 3.6V 10 3.3V 3.0V 8 Icc [mA] 33.3.1.1 2.7V 6 4 2.2V 1.
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Figure 33-87. Active supply current vs. VCC. fSYS = 32.768kHz internal RC. Icc [µA] 300 250 -40°C 200 25°C 85°C 150 100 50 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-88. Active supply current vs. VCC. fSYS = 1.0MHz external clock. 1000 -40°C 900 25°C 800 85°C I CC [µA] 700 600 500 400 300 200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-89. Active supply current vs. VCC. fSYS = 2.0MHz internal RC. 1600 -40°C 25°C 85°C 1400 1200 Icc [µA] 1000 800 600 400 200 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-90. Active supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 6 -40°C 25°C 85°C 5 Icc [mA] 4 3 2 1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-91. Active supply current vs. VCC. fSYS = 32MHz internal RC. 13 -40°C 12 25°C 85°C 11 Icc [mA] 10 9 8 7 6 5 4 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Idle supply current Figure 33-92. Idle supply current vs. frequency. fSYS = 0 - 1.0MHz, T = 25°C. 140 3.6V 120 3.3V 100 Icc [µA] 33.3.1.2 3.0V 80 2.7V 60 2.2V 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-93. Idle supply current vs. frequency. fSYS = 1 - 32MHz, T = 25°C. Icc [mA] 4.5 4.0 3.6V 3.5 3.3V 3.0 3.0V 2.5 2.7V 2.0 1.5 2.2V 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-94. Idle supply current vs. VCC. fSYS = 32.768kHz internal RC. 32 85°C 31 -40°C 30 25°C Icc [µA] 29 28 27 26 25 24 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-95. Idle supply current vs. VCC. fSYS = 1.0MHz external clock. 140 85°C 25°C -40°C 120 Icc [µA] 100 80 60 40 20 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-96. Idle supply current vs. VCC. fSYS = 2.0MHz internal RC. 400 85°C 350 25°C -40°C Icc [µA] 300 250 200 150 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-97. Idle supply current vs. VCC. fSYS = 32MHz internal RC prescaled to 8MHz. 1800 -40°C 25°C 85°C 1600 Icc [µA] 1400 1200 1000 800 600 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-98. Idle supply current vs. VCC. fSYS = 32MHz internal RC. 5.0 -40°C Icc [mA] 4.5 25°C 85°C 4.0 3.5 3.0 2.5 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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Power-down supply current Figure 33-99. Power-down supply current vs. VCC. All functions disabled. 2.5 85°C Icc [µA] 2 1.5 1 0.5 25°C -40°C 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-100. Power-down supply current vs. VCC. Watchdog and sampled BOD enabled. 2.5 85°C 2 Icc [µA] 33.3.1.3 1.5 1 0.5 25°C -40°C 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-101. Power-down supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 2 3.3V 1.8 2.7V 1.6 1.8V Icc [µA] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.3.2 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Pull-up Figure 33-102.
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Figure 33-103. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 100 ICC [µA] 80 60 40 -40°C 25°C 20 85°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 33-104. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 120 I CC [µA] 100 80 60 -40°C 40 25°C 20 85°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Output voltage vs. sink/source current Figure 33-105. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 V PIN [V] 1.4 1.2 - 40°C 1.0 0.8 25°C 0.6 85°C 0.4 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 IPIN [mA] Figure 33-106. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 3 2.5 V PIN [V] 33.3.2.2 2 -40°C 1.5 25°C 1 85°C 0.
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Figure 33-107. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3 V PIN [V] 2.5 2 -40°C 1.5 25 °C 1 85°C 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-108. I/O pin output voltage vs. sink current. VCC = 1.8V. 2.0 1.8 85°C 1.6 V PIN [V] 1.4 1.2 1.0 0.8 25°C 0.6 -40°C 0.4 0.
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Figure 33-109. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.2 1 85°C 25°C V PIN [V] 0.8 -40°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-110. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.4 1.2 85°C 1 25°C V PIN [V] -40°C 0.8 0.6 0.4 0.
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Thresholds and hysteresis Figure 33-111. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 2 -40°C Vthreshold [V] 1.8 25°C 85°C 1.6 1.4 1.2 1 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-112. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.7 -40°C 25°C 85°C 1.5 Vthreshold [V] 33.3.2.3 1.3 1.1 0.9 0.7 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-113. I/O pin input hysteresis vs. VCC. 0.4 0.375 0.35 Vthreshold [V] 0.325 0.3 0.275 0.25 -40°C 0.225 25°C 0.2 85°C 0.175 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.3.3 ADC characteristics Figure 33-114. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-115. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-116. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-117. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-118. I/O pin input threshold voltage vs. VCC. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.
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Figure 33-119. DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-120. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-121. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-122. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-123. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. -3 Gain error [mV] -4 -5 Single-ended signed mode -6 -7 Differential mode -8 -9 -10 Single-ended unsigned mode -11 -12 -13 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-124. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.
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33.3.4 Analog Comparator characteristics Figure 33-125. Analog comparator hysteresis vs. VCC. Small hysteresis. 19 18 85°C VHYST [mV] 17 16 25°C 15 14 -40°C 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-126. Analog comparator hysteresis vs. VCC. Large hysteresis. 36 85°C 34 VHYST [mV] 32 25°C 30 28 -40°C 26 24 22 20 18 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-127. Analog comparator current source vs. calibration value. VCC = 3.0V. 7 ICURRENTSOURCE [µA] 6.5 6 5.5 5 4.5 -40°C 25°C 85°C 4 3.5 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-128. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.6 0.55 25°C 0.5 INL[LSB] 0.45 0.4 0.35 0.3 0.25 0.2 0.
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33.3.5 Internal 1.0V reference characteristics Figure 33-129. ADC internal 1.0V reference vs. temperature. 1.007 1.006 Bandgap Voltage [V] 1.005 1.004 1.003 1.002 1.6V 1.001 1.000 2.7V 0.999 3.6V 0.998 0.997 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [ ° C] 33.3.6 BOD characteristics Figure 33-130. BOD thresholds vs. temperature. BOD level = 1.6V. 1.596 1.594 Rising Vcc VBOT [V] 1.592 1.59 1.588 1.586 Falling Vcc 1.584 1.
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Figure 33-131. BOD thresholds vs. temperature. BOD level = 3.0V. 3.05 Rising Vcc 3.04 V BOT [V] 3.03 3.02 3.01 Falling Vcc 3 2.99 2.98 0 10 20 30 40 50 60 70 80 Temperature [°C] External reset characteristics Figure 33-132. Minimum reset pin pulse width vs. VCC. 140 135 130 125 120 t RST [ns] 33.3.7 115 110 105 85°C 100 25°C 95 -40°C 90 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-133. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 -40°C 25°C 20 85°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Figure 33-134. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 140 120 IRESET [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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Figure 33-135. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 120 IRESET [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 VRESET [V] Figure 33-136. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 85°C 25°C -40 °C 1.6 VTHRESHOLD [V] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.3.8 Oscillator characteristics 33.3.8.1 Ultra low-power internal oscillator Figure 33-137. Ultra low-power internal oscillator frequency vs. temperature. 36 35.5 Frequency [MHz] 35 34.5 34 33.5 3.6V 3.3V 33 3.0V 2.7V 1.8V 32.5 32 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 32.768kHz internal oscillator Figure 33-138. 32.768kHz internal oscillator frequency vs. temperature. 1.8V 2.2V 2.7V 3.0V 3.3V 3.6V 32.8 32.75 32.7 Frequency [kHz] 33.3.8.2 32.65 32.6 32.
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Figure 33-139. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 3.0V 47 Frequency [kHz] 44 41 38 35 32 29 26 23 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 RC32KCAL[7..0] 2MHz internal oscillator Figure 33-140. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 2.12 Frequency [MHz] 33.3.8.3 2.1 2.08 2.06 2.04 3.3V 3.0V 2.02 2 2.7V 1.98 2.2V 1.8V 1.
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Frequency [MHz] Figure 33-141. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.678kHz internal oscillator. 2.005 1.8V 2.2V 2 2.7V 3.0V 1.995 3.3V 1.99 1.985 1.98 1.975 1.97 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-142. 2MHz internal oscillator frequency vs. CALA calibration value. VCC = 3.0V. Frequecncy[MHz] 2.5 2.4 -40°C 2.3 25°C 2.2 85°C 2.1 2 1.9 1.8 1.
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32MHz internal oscillator Figure 33-143. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35 Frequency [MHz] 34.5 34 33.5 33 3.3V 3.0V 32.5 2.7V 2.2V 1.8V 32 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-144. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.678kHz internal oscillator. 32.1 1.8V 2.2V 32.05 32 Frequency [MHz] 33.3.8.4 2.7V 3.0V 3.3V 31.95 31.9 31.85 31.8 31.75 31.7 31.65 31.
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Figure 33-145. 32MHz internal oscillator CALA calibration step value. VCC = 3.0V. 0.28 0.26 Step size [%] 0.24 0.22 0.20 -40°C 25°C 0.18 0.16 85°C 0.14 0.12 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 CALA Figure 33-146. 32MHz internal oscillator frequency vs. CALB calibration step value. VCC = 3.0V.
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32MHz internal oscillator calibrated to 48MHz Figure 33-147. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 Frequency [MHz] 53 52 51 50 3.6V 49 3.3V 48 3.0V 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 2.7V 1.8V Temperature [°C] Figure 33-148. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.678kHz internal oscillator. 48.1 1.8V 2.7V 3.0V 3.3V 3.6V 48 47.9 Frequency [MHz] 33.3.8.5 47.8 47.7 47.6 47.5 47.4 47.3 47.
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33.3.9 Two-wire interface characteristics Figure 33-149. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-150. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.3.10 PDI characteristics Figure 33-151. Maximum PDI frequency vs. VCC. 23 -40°C 21 fMAX [MHz] 19 25°C 85°C 17 15 13 11 9 7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.4 Atmel ATxmega192D3 33.4.1 Current consumption Active mode supply current Figure 33-152. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 650 3.3V ICC [µA] 600 550 3.0V 500 450 2.7V 400 350 300 250 2.2V 1.8V 200 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 33-153. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.3V 9 3.0V 8 ICC [mA] 33.4.1.1 2.7V 7 6 5 4 2.2V 3 2 1.
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Figure 33-154. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40°C 240 25°C 210 ICC [µA] 85°C 180 150 120 90 60 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-155. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 750 -40°C 25°C 85°C 700 650 ICC [µA] 600 550 500 450 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-156. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1500 -40°C 25°C 85°C 1400 1300 1200 ICC [µA] 1100 1000 900 800 700 600 500 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 33-157. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.0 5.5 -40°C 25°C 85°C 5.0 ICC [mA] 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-158. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 14 -40°C 13 25°C 12 ICC [mA] 85°C 11 10 9 8 7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] Idle mode supply current Figure 33-159. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 130 3.3V 117 ICC [µA] 33.4.1.2 104 3.0V 91 2.7V 78 65 2.2V 52 1.8V 39 26 13 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 33-160. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.3V 3.5 3.0V ICC [mA] 3.0 2.7V 2.5 2.0 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-161. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 33 85°C 32 31 ICC [µA] -40°C 30 25°C 29 28 27 26 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-162. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 160 85°C 25°C -40°C 140 ICC [µA] 120 100 80 60 40 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-163. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 390 -40°C 25°C 85°C 360 ICC [µA] 330 300 270 240 210 180 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-164. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2000 -40°C 25°C 85°C 1800 ICC [µA] 1600 1400 1200 1000 800 600 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-165. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.50 -40°C 5.25 25°C 5.00 85°C ICC [mA] 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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Power-down mode supply current Figure 33-166. Power-down mode supply current vs. VCC. All functions disabled. 4.5 85°C 4.0 3.5 ICC [µA] 3.0 2.5 2.0 1.5 1.0 0.5 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-167. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.0 85°C 4.5 4.0 ICC [µA] 33.4.1.3 3.5 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-168. Power-down mode supply current vs. temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 4.5 3.0V 2.7V 2.2V 1.8V 4.0 3.5 ICC [µA] 3.0 2.5 2.0 1.5 1.0 0.5 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.4.2 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Pull-up Figure 33-169.
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Figure 33-170. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 24 -40°C 25°C 85°C 12 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-171. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 -40°C 25°C 85°C 28 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Output voltage vs. sink/source current Figure 33-172. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN[V] 1.4 1.2 1.0 25°C -40°C 0.8 0.6 85°C 0.4 0.2 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 IPIN [mA] Figure 33-173. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 3.0 2.5 VPIN[V] 33.4.2.2 2.0 -40°C 1.5 85°C 25°C 1.0 0.
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Figure 33-174. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-175. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 85°C 0.9 25°C 0.8 VPIN [V] 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-176. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85°C 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-177. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 25°C 0.9 -40°C 0.8 VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Thresholds and hysteresis Figure 33-178. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85°C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-179. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.6 -40°C 85°C 25°C 1.5 1.4 Vthreshold [V] 33.4.2.3 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-180. I/O pin input hysteresis vs. VCC. 0.42 0.39 Vthreshold [V] 0.36 0.33 0.30 0.27 0.24 -40°C 0.21 25°C 0.18 85°C 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.4.3 ADC characteristics Figure 33-181. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-182. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.70 Single-ended unsigned mode 0.65 INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 Single-ended signed mode 0.35 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-183. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-184. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-185. DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.
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Figure 33-186. DNL error vs. input code. 1.0 0.8 DNL [LSB] 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-187. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. -5 -6 Gain error [mV] -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-188. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 -6 Single-ended signed mode -7 Single-ended unsigned mode -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-189. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 9.0 Offset error [mV] 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-190. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. -3 Single-ended signed mode -4 Gain error [mV] -5 -6 -7 Differential mode -8 -9 -10 -11 Single-ended unsigned mode -12 -13 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-191. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.
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33.4.4 Analog comparator characteristics Figure 33-192. Analog comparator hysteresis vs. VCC. Small hysteresis. 19 18 85°C VHYST [mV] 17 16 25°C 15 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-193. Analog comparator hysteresis vs. VCC. Large hysteresis. 36 85°C 34 VHYST [mV] 32 25°C 30 28 -40°C 26 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-194. Analog comparator current source vs. calibration value. VCC = 3.0V. 8 7 I [µA] 6 5 3.6V 4 3.0V 2.4V 3 2.0V 1.6V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 33-195. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.39 0.36 INL [LSB] 0.33 0.30 25°C 0.27 0.24 0.21 0.18 0.
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33.4.5 Internal 1.0V reference characteristics Figure 33-196. ADC Internal 1.0V reference vs. temperature. 1.012 Bandgap Voltage [V] 1.010 1.008 1.006 1.004 1.002 1.8V 2.7V 3.0V 1.000 0.998 0.996 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 35 45 55 65 75 85 Temperature [°C] 33.4.6 BOD characteristics Figure 33-197. BOD thresholds vs. temperature. BOD level = 1.6V. 1.626 1.624 VBOT [V] 1.622 1.620 1.618 1.616 1.614 1.
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Figure 33-198. BOD thresholds vs. temperature. BOD level = 3.0V. 3.09 3.08 VBOT [V] 3.07 3.06 3.05 3.04 3.03 3.02 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.4.7 External reset characteristics Figure 33-199. Minimum reset pin pulse width vs. VCC. 140 135 130 125 tRST [ns] 120 115 110 105 100 85°C 95 25°C -40°C 90 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-200. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 33-201. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IRESET[µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
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Figure 33-202. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IRESET [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] Figure 33-203. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 85°C 25°C -40°C VTHRESHOLD [V] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.4.8 Oscillator characteristics 33.4.8.1 Ultra Low-Power internal oscillator Figure 33-204. Ultra Low-Power internal oscillator frequency vs. temperature. 34.0 Frequency [kHz] 33.5 33.0 32.5 32.0 3.6V 3.0V 2.7V 1.8V 31.5 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 32.768kHz internal oscillator Figure 33-205. 32.768kHz internal oscillator frequency vs. temperature. 32.85 1.8V 2.2V 2.7V 3.0V 3.6V 3.3V 32.80 32.75 Frequency [kHz] 33.4.8.2 32.70 32.65 32.
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Figure 33-206. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 3.0V 47 Frequency [kHz] 44 41 38 35 32 29 26 23 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 2MHz internal oscillator Figure 33-207. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.18 2.16 2.14 Frequency [MHz] 33.4.8.3 2.12 2.10 2.08 2.06 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.04 2.02 2.00 1.
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Figure 33-208. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 2.005 1.8V 2.2V 2.7V 3.0V 3.6V 3.3V Frequency [MHz] 2.000 1.995 1.990 1.985 1.980 1.975 1.970 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-209. 2MHz internal oscillator frequency vs. CALA calibration value. VCC = 3V. 2.5 -40°C Frequency [MHz] 2.4 25°C 2.3 85°C 2.2 2.1 2.0 1.9 1.8 1.
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32MHz internal oscillator Figure 33-210. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35.0 Frequency [MHz] 34.5 34.0 33.5 33.0 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-211. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.3V 3.0V 2.7V 2.2V 1.8V 32.05 32.00 Frequency [MHz] 33.4.8.4 31.95 31.90 31.85 31.80 31.75 31.
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Figure 33-212. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.37 0.34 Step size [%] 0.31 0.28 0.25 0.22 0.19 -40°C 0.16 85°C 25°C 0.13 0.10 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 33-213. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
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32MHz internal oscillator calibrated to 48MHz Figure 33-214. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 Frequency [MHz] 53 52 51 50 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-215. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.1 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 48.0 Frequency [MHz] 33.4.8.5 47.9 47.8 47.7 47.6 47.5 47.4 47.
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33.4.9 Two-wire interface characteristics Figure 33-216. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-217. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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PDI characteristics Figure 33-218. Maximum PDI frequency vs. VCC. 23 -40°C 21 19 fMAX [MHz] 33.4.10 25°C 85°C 17 15 13 11 9 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.5 Atmel ATxmega256D3 33.5.1 Current consumption Active mode supply current Figure 33-219. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 650 3.3V ICC [µA] 600 550 3.0V 500 450 2.7V 400 350 300 250 2.2V 1.8V 200 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 33-220. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.3V 9 3.0V 8 ICC [mA] 33.5.1.1 2.7V 7 6 5 4 2.2V 3 2 1.
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Figure 33-221. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40°C 240 25°C 210 ICC [µA] 85°C 180 150 120 90 60 30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-222. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 750 -40°C 25°C 85°C 700 650 ICC [µA] 600 550 500 450 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-223. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1500 -40°C 25°C 85°C 1400 1300 1200 ICC [µA] 1100 1000 900 800 700 600 500 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 33-224. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.0 5.5 -40°C 25°C 85°C 5.0 ICC [mA] 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-225. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 14 -40°C 13 25°C 12 ICC [mA] 85°C 11 10 9 8 7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] Idle mode supply current Figure 33-226. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 130 3.3V 117 ICC [µA] 33.5.1.2 104 3.0V 91 2.7V 78 65 2.2V 52 1.8V 39 26 13 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 33-227. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.3V 3.5 3.0V ICC [mA] 3.0 2.7V 2.5 2.0 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-228. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 33 85°C 32 31 ICC [µA] -40°C 30 25°C 29 28 27 26 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-229. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 160 85°C 25°C -40°C 140 ICC [µA] 120 100 80 60 40 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-230. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 390 -40°C 25°C 85°C 360 ICC [µA] 330 300 270 240 210 180 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-231. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2000 -40°C 25°C 85°C 1800 ICC [µA] 1600 1400 1200 1000 800 600 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-232. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.50 -40°C 5.25 25°C 5.00 85°C ICC [mA] 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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Power-down mode supply current Figure 33-233. Power-down mode supply current vs. VCC. All functions disabled. 4.5 85°C 4.0 3.5 ICC [µA] 3.0 2.5 2.0 1.5 1.0 0.5 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-234. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.0 85°C 4.5 4.0 ICC [µA] 33.5.1.3 3.5 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-235. Power-down mode supply current vs. temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 4.5 3.0V 2.7V 2.2V 1.8V 4.0 3.5 ICC [µA] 3.0 2.5 2.0 1.5 1.0 0.5 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.5.2 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Pull-up Figure 33-236.
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Figure 33-237. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 24 -40°C 25°C 85°C 12 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-238. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 -40°C 25°C 85°C 28 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Output voltage vs. sink/source current Figure 33-239. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN[V] 1.4 1.2 1.0 25°C -40°C 0.8 0.6 85°C 0.4 0.2 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 IPIN [mA] Figure 33-240. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 3.0 2.5 VPIN[V] 33.5.2.2 2.0 -40°C 1.5 85°C 25°C 1.0 0.
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Figure 33-241. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-242. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 85°C 0.9 25°C 0.8 VPIN [V] 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-243. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85°C 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-244. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 25°C 0.9 -40°C 0.8 VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Thresholds and hysteresis Figure 33-245. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85°C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-246. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.6 -40°C 85°C 25°C 1.5 1.4 Vthreshold [V] 33.5.2.3 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-247. I/O pin input hysteresis vs. VCC. 0.42 0.39 Vthreshold [V] 0.36 0.33 0.30 0.27 0.24 -40°C 0.21 25°C 0.18 85°C 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.5.3 ADC characteristics Figure 33-248. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-249. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.70 Single-ended unsigned mode 0.65 INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 Single-ended signed mode 0.35 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-250. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-251. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-252. DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.
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Figure 33-253. DNL error vs. input code. 1.0 0.8 DNL [LSB] 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-254. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. -5 -6 Gain error [mV] -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-255. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 -6 Single-ended signed mode -7 Single-ended unsigned mode -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-256. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 9.0 Offset error [mV] 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-257. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. -3 Single-ended signed mode -4 Gain error [mV] -5 -6 -7 Differential mode -8 -9 -10 -11 Single-ended unsigned mode -12 -13 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-258. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.
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33.5.4 Analog comparator characteristics Figure 33-259. Analog comparator hysteresis vs. VCC. Small hysteresis. 19 18 85°C VHYST [mV] 17 16 25°C 15 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-260. Analog comparator hysteresis vs. VCC. Large hysteresis. 36 85°C 34 VHYST [mV] 32 25°C 30 28 -40°C 26 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-261. Analog comparator current source vs. calibration value. VCC = 3.0V. 8 7 I [µA] 6 5 3.6V 4 3.0V 2.4V 3 2.0V 1.6V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 33-262. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.39 0.36 INL [LSB] 0.33 0.30 25°C 0.27 0.24 0.21 0.18 0.
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33.5.5 Internal 1.0V reference characteristics Figure 33-263. ADC Internal 1.0V reference vs. temperature. 1.012 Bandgap Voltage [V] 1.010 1.008 1.006 1.004 1.002 1.8V 2.7V 3.0V 1.000 0.998 0.996 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 35 45 55 65 75 85 Temperature [°C] 33.5.6 BOD characteristics Figure 33-264. BOD thresholds vs. temperature. BOD level = 1.6V. 1.626 1.624 VBOT [V] 1.622 1.620 1.618 1.616 1.614 1.
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Figure 33-265. BOD thresholds vs. temperature. BOD level = 3.0V. 3.09 3.08 VBOT [V] 3.07 3.06 3.05 3.04 3.03 3.02 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.5.7 External reset characteristics Figure 33-266. Minimum reset pin pulse width vs. VCC. 140 135 130 125 tRST [ns] 120 115 110 105 100 85°C 95 25°C -40°C 90 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-267. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 33-268. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IRESET[µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
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Figure 33-269. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IRESET [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] Figure 33-270. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 85°C 25°C -40°C VTHRESHOLD [V] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.5.8 Oscillator characteristics 33.5.8.1 Ultra Low-Power internal oscillator Figure 33-271. Ultra Low-Power internal oscillator frequency vs. temperature. 34.0 Frequency [kHz] 33.5 33.0 32.5 32.0 3.6V 3.0V 2.7V 1.8V 31.5 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 32.768kHz internal oscillator Figure 33-272. 32.768kHz internal oscillator frequency vs. temperature. 32.85 1.8V 2.2V 2.7V 3.0V 3.6V 3.3V 32.80 32.75 Frequency [kHz] 33.5.8.2 32.70 32.65 32.
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Figure 33-273. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 3.0V 47 Frequency [kHz] 44 41 38 35 32 29 26 23 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 2MHz internal oscillator Figure 33-274. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.18 2.16 2.14 Frequency [MHz] 33.5.8.3 2.12 2.10 2.08 2.06 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.04 2.02 2.00 1.
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Figure 33-275. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.005 1.8V 2.2V 2.7V 3.0V 3.6V 3.3V Frequency [MHz] 2.000 1.995 1.990 1.985 1.980 1.975 1.970 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-276. 2MHz internal oscillator frequency vs. CALA calibration value. VCC = 3V. 2.5 -40°C Frequency [MHz] 2.4 25°C 2.3 85°C 2.2 2.1 2.0 1.9 1.8 1.
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32MHz internal oscillator Figure 33-277. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35.0 Frequency [MHz] 34.5 34.0 33.5 33.0 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-278. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.3V 3.0V 2.7V 2.2V 1.8V 32.05 32.00 Frequency [MHz] 33.5.8.4 31.95 31.90 31.85 31.80 31.75 31.
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Figure 33-279. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.37 0.34 Step size [%] 0.31 0.28 0.25 0.22 0.19 -40°C 0.16 85°C 25°C 0.13 0.10 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 33-280. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
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32MHz internal oscillator calibrated to 48MHz Figure 33-281. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 Frequency [MHz] 53 52 51 50 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-282. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.1 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 48.0 Frequency [MHz] 33.5.8.5 47.9 47.8 47.7 47.6 47.5 47.4 47.
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33.5.9 Two-wire interface characteristics Figure 33-283. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-284. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.5.10 PDI characteristics Figure 33-285. Maximum PDI frequency vs. VCC. 23 -40°C 21 fMAX [MHz] 19 25°C 85°C 17 15 13 11 9 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.6 Atmel ATxmega384D3 33.6.1 Current consumption Active mode supply current Figure 33-286. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [µA] 1200 1100 3.6V 1000 3.3V 900 3.0V 800 2.7V 700 600 2.2V 500 1.8V 400 300 200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-287. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.6V 12 3.3V 10 ICC [mA] 33.6.1.1 3.0V 2.7V 8 6 2.2V 4 1.
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Figure 33-288. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 500 -40°C 450 400 25°C ICC [µA] 350 85°C 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 33-289. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 1300 1200 -40°C 1100 25°C 85°C Icc [µA] 1000 900 800 700 600 500 400 300 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-290. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 650 85°C 600 25°C 550 -40°C ICC [µA] 500 450 400 350 300 250 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-291. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 -40°C 6.0 25°C 5.5 85°C ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-292. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 10 85°C 25°C 9 -40°C ICC [mA] 8 7 6 5 4 3 2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Idle mode supply current Figure 33-293. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 140 3.6V ICC [µA] 33.6.1.2 120 3.3V 100 3.0V 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-294. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.5 3.6V 4.0 3.3V 3.5 ICC [mA] 3.0V 3.0 2.7V 2.5 2.0 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-295. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 37 85°C 36 35 Icc [µA] 34 -40°C 33 32 25°C 31 30 29 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-296. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 150 85°C 25°C -40°C 140 130 120 ICC [µA] 110 100 90 80 70 60 50 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-297. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 400 -40°C 25°C 85°C 375 350 ICC [µA] 325 300 275 250 225 200 175 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-298. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1900 -40°C 25°C 85°C 1700 ICC [µA] 1500 1300 1100 900 700 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-299. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5250 5000 -40°C 4750 25°C 4500 85°C ICC [µA] 4250 4000 3750 3500 3250 3000 2750 2500 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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Power-down mode supply current Figure 33-300. Power-down mode supply current vs. VCC. All functions disabled. 4.5 85°C 4.0 3.5 3.0 ICC [µA] 2.5 2.0 1.5 1.0 0.5 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-301. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 7 85°C 6 5 Icc [µA] 33.6.1.3 4 3 2 25°C -40°C 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-302. Power-down mode supply current vs. temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7 6 3.0V 2.7V 2.2V 1.8V Icc [µA] 5 4 3 2 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.6.2 I/O pin characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Pull-up Figure 33-303.
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Figure 33-304. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 24 -40°C 25°C 85°C 12 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-305. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 -40°C 25°C 85°C 28 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
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Output voltage vs. sink/source current Figure 33-306. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 -40°C 0.6 25°C 85°C 0.4 0.2 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 I PIN [mA] Figure 33-307. I/O pin output voltage vs. source current. VCC = 3.0V. 3.5 3.0 2.5 VPIN [V] 33.6.2.2 2.0 1.5 1.0 -40°C 25°C 85°C 0.
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Figure 33-308. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN[V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-309. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 85°C 0.9 0.8 25°C VPIN [V] 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-310. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85°C VPIN [V] 0.9 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-311. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 25°C 85°C 0.9 -40°C 0.8 VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Thresholds and hysteresis Figure 33-312. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 85°C 25°C -40°C 1.7 1.6 Vthreshold [V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-313. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.6 85°C 25°C -40°C 1.5 1.4 1.3 Vthreshold [V] 33.6.2.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-314. I/O pin input hysteresis vs. VCC. 0.42 0.39 0.36 Vthreshold [V] 0.33 0.30 0.27 0.24 -40°C 25°C 85°C 0.21 0.18 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.6.3 ADC characteristics Figure 33-315. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-316. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode 0.60 INL[LSB] 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-317. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-318. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-319. DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 Differential mode 0.40 0.35 Single-ended signed mode 0.30 0.25 0.
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Figure 33-320. DNL error vs. input code. 1.0 0.8 DNL [LSB] 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-321. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. -5 -6 Gain error [mV] -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-322. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. -2 Gain error [mV] -3 -4 Differential mode -5 -6 Single-ended signed mode -7 Single-ended unsigned mode -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] Figure 33-323. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps. 9.4 9.2 9.0 Offset error [mV] 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-324. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. -3 Single-ended signed mode -4 Gain error [mV] -5 -6 -7 Differential mode -8 -9 -10 -11 Single-ended unsigned mode -12 -13 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-325. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sample rate = 300ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.
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33.6.4 Analog comparator characteristics Figure 33-326. Analog comparator hysteresis vs. VCC. Small hysteresis. 19 18 85°C 17 VHYST [mV] 16 25°C 15 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-327. Analog comparator hysteresis vs. VCC. Large hysteresis. 36 34 85°C VHYST [mV] 32 30 25°C 28 -40°C 26 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-328. Analog comparator current source vs. calibration value. VCC = 3.0V. 8 7 I [µA] 6 5 3.6V 4 3.0V 3 2.4V 2.0V 1.6V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA[3..0] Figure 33-329. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.44 25°C 0.41 INL [LSB] 0.38 0.35 0.32 0.29 0.26 0.23 0.
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33.6.5 Internal 1.0V reference characteristics Figure 33-330. ADC Internal 1.0V reference vs. temperature. 1.035 Bandgap voltage [V] 1.030 1.025 1.020 1.015 1.010 1.005 1.6V 2.4V 3.6V 1.000 0.995 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 35 45 55 65 75 85 Temperature [°C] 33.6.6 BOD characteristics Figure 33-331. BOD thresholds vs. temperature. BOD level = 1.6V. 1.78 1.74 VBOT [V] 1.70 1.66 1.62 1.58 1.54 1.
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Figure 33-332. BOD thresholds vs. temperature. BOD level = 3.0V. 3.30 3.25 VBOT [V] 3.20 3.15 3.10 3.05 3.00 2.95 2.90 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 33.6.7 External reset characteristics Figure 33-333. Minimum reset pin pulse width vs. VCC. 135 130 125 120 tRST [ns] 115 110 105 100 85°C 95 90 25°C -40°C 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-334. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V RESET [V] Figure 33-335. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IRESET[µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
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Figure 33-336. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IRESET [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V RESET [V] Figure 33-337. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 85°C 25°C -40°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.6.8 Oscillator characteristics 33.6.8.1 Ultra Low-Power internal oscillator Figure 33-338. Ultra Low-Power internal oscillator frequency vs. temperature. 35.5 Frequency [kHz] 35.0 34.5 34.0 33.0 33.0 3.6V 3.0V 2.7V 1.8V 32.5 32.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 32.768kHz internal oscillator Figure 33-339. 32.768kHz internal oscillator frequency vs. temperature. 32.84 1.8V 32.81 2.2V 2.7V 3.0V 3.6V 3.3V 32.78 Frequency [kHz] 33.6.8.2 32.75 32.
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Figure 33-340. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 53 3.0V 50 Frequency [kHz] 47 44 41 38 35 32 29 26 23 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 2MHz internal oscillator Figure 33-341. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.20 2.18 2.16 2.14 Frequency [MHz] 33.6.8.3 2.12 2.10 2.08 2.06 3.3V 3.0V 2.7V 2.2V 1.8V 2.04 2.02 2.00 1.
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Figure 33-342. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . Frequency [MHz] 2.010 2.008 3.3V 2.006 3.0V 2.004 2.7V 2.2V 2.002 1.8V 2.000 1.998 1.996 1.994 1.992 1.990 1.988 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-343. 2MHz internal oscillator frequency vs. CALA calibration value. VCC = 3V. 2.6 -40°C 2.5 Frequency [MHz] 2.4 25°C 2.3 85°C 2.2 2.1 2.0 1.9 1.8 1.
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32MHz internal oscillator Figure 33-344. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 37.0 36.5 Frequency [MHz] 36.0 35.5 35.0 34.5 34.0 33.5 3.3V 3.0V 2.7V 2.2V 1.8V 33.0 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-345. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.09 1.8V 2.2V 32.06 32.03 Frequency [MHz] 33.6.8.4 2.7V 3.0V 3.3V 32.00 31.97 31.94 31.
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Figure 33-346. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.39 0.36 Step size:[%] 0.33 0.30 -40°C 0.27 0.24 0.21 25°C 0.18 85°C 0.15 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 33-347. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
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32MHz internal oscillator calibrated to 48MHz Figure 33-348. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55 Frequency [MHz] 54 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-349. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.2 1.8V 2.2V 48.1 Frequency [MHz] 33.6.8.5 2.7V 3.0V 3.3V 48.0 47.9 47.8 47.7 47.
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33.6.9 Two-wire interface characteristics Figure 33-350. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-351. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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PDI characteristics Figure 33-352. fMAX [MHz] 33.6.10 Maximum PDI frequency vs. VCC. 36 -40°C 31 25°C 85°C 26 21 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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34. Errata 34.1 Atmel ATxmega32D3 34.1.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
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34.2 Atmel ATxmega64D3 34.2.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
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34.2.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-1.Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
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— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-1. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17.
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if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.
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 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.
PAGE 365
34.2.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-2. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
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— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-2. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
PAGE 369
16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.
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Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.
PAGE 371
 CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in
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34.3 Atmel ATxmega128D3 34.3.1 Rev. J  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
PAGE 373
34.3.6 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-3. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
PAGE 375
— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
PAGE 376
Problem fix/Workaround Table 34-3. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
PAGE 377
16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17.
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if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.
PAGE 379
 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.
PAGE 380
34.3.9 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-4. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
PAGE 382
— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
PAGE 383
Problem fix/Workaround Table 34-4. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
PAGE 384
16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.
PAGE 385
Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.
PAGE 386
 CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in
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34.4 Atmel ATxmega192D3 34.4.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
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34.4.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-5. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
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— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-5. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17.
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if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.
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 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.
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34.4.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-6. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
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— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-6. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.
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Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.
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25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.
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34.4.9 Rev. A Not sampled.
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34.5 Atmel ATxmega256D3 34.5.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators.
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34.5.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-7. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
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— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Table 34-7. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 12.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17.
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if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.
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 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.
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34.5.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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Figure 34-8. Analog comparator voltage scaler vs. scalefac. T = 25°C. 3.5 3.3V 3.0 2.7V VSCALE [V] 2.5 2.0 1.8V 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from software or event system.
PAGE 413
— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-8. Configure PWM and CWCM according to this table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
PAGE 415
16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.
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Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.
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25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.
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34.5.9 Rev. A Not sampled.
PAGE 419
34.6 Atmel ATxmega384D3 34.6.1 Rev. B  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator.
PAGE 420
35. Datasheet revision history Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 8134N – 03/2014 1. Updated Table 28-2 on page 51. PORT PB1 has PIN# 7 2. Updated Table 32-5 on page 66 and Table 32-34 on page 85: The condition for ADC updated from 200ksps to 16ksps, VREF = Ext. ref 3.
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35.5 8134J – 03/2013 1. Almost all figures in Chapter “Typical characteristics” are updated. 2. Added new Errata “Rev. G” on page 117. 3. Added new Errata “Rev. B” on page 125 and “Rev. E” on page 118. Non available functions and options. 4. Editing updates. 5. Added ATxmega32D3 and ATxmega384D3. 6. New datasheet template is added. 7. A lot of small corrections and a complete reorganization of “Electrical characteristics” and “Typical characteristics” . 8.
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35.6 35.7 8134I – 12/2010 1. Datasheet status changed to complete: Preliminary removed from front page. 2. Updated all tables in the The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. on page 64 3. Replaced Table 31-11 on page 67. 4. Replaced Table 31-17 on page 68 and added the figure “TOSC input capacitance” on page 78. 5. Added “Rev. E” on page 118. 6.
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4. Updated “Alternate pin function description” on page 49. 5. Updated “Alternate pin functions” on page 50. 6. Updated “Timer/counter and AWEX functions” on page 49. 7. Added Table 31-17 on page 68. 8. Added Table 31-18 on page 69. 9. Changed internal oscillator speed to “Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode.” on page 108 10. Updated “Errata” on page 356. 35.11 8134D – 11/2009 1. Added Table 31-3 on page 64, Endurance and data retention 2.
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35.14 8134A – 03/2009 1. Initial revision.
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11. System control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.1 11.2 11.3 11.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset sources . . . . . . . . . . . . . . . . . . . .
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23. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 42 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24. CRC – Cyclic Redundancy Check generator . . . . . . . . . . . . . . . . . . 43 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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34.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 35. Datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 35.1 35.2 35.3 35.4 35.5 35.6 35.7 35.8 35.9 35.10 35.11 35.12 35.13 35.14 8134N – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8134M – 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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XMEGA D3 [DATASHEET] Atmel-8134N-AVR-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014 v
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