Datasheet

417
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
25. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or config-
ure these functions or options will have no effect, and will be as writing to a reserved address location.
 TWIE, the TWI module on PORTE
 TWI SDAHOLD option in the TWI CTRL register is one bit
 CRC generator module
 ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
 ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
 ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
 ADC channel scan and the ADC SCAN register
 ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
 ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
 Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
 Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
 PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
 PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register.
 TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
 Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
 PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
 PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
 The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
 The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/Workaround
None.
26. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
27. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None