Datasheet

5
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
3.1 Block Diagram
Figure 3-1. XMEGA A3U block diagram.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
DMA
Controller
SRAM
ADCA
ACA
DACB
ADCB
ACB
OCD
PDI
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
DES
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7] PE[0..7]
PORT D (8)
TCD0:1
USARTD0:1
SPID
TCE0:1
USARTE0:1
TWIE
SPIE
PORT E (8)
AES
USB
PORT R (2)
XTAL1
XTAL2
PR[0..1]
DATA BUS
NVM Controller
MORPEEhsalF
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
TCF0
USARTF0
PF[0..7]
PORT F (8)
EVENT ROUTING NETWORK
To Clock
Generator
Int. Refs.
Tempref
Digital function
Analog function
Programming, debug, test
Oscillator/Crystal/Clock
General Purpose I/O