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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 (9x9) 8/16-Bit 32 MHz I/O number 50

Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 64K - 256KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 2K - 4KBytes EEPROM

 4K - 16KBytes internal SRAM

 Peripheral features

 Four-channel DMA controller

 Eight-channel event system

 Seven 16-bit timer/counters

 Four timer/counters with four output compare or input capture channels

 Three timer/counters with two output compare or input capture

channels

 High resolution extension on all timer/counters

 Advanced waveform extension (AWeX) on one timer/counter

 One USB device interface

 USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device

compliant

 32 Endpoints with full configuration flexibility

 Seven USARTs with IrDA support for one USART

 Two two-wire interfaces with dual address match (I

C and SMBus compatible)

 Three serial peripheral interfaces (SPIs)

 AES and DES crypto engine

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE

802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters

 One two-channel, 12-bit, 1msps Digital to Analog Converter

 Four Analog Comparators with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interfaces

 JTAG (IEEE 1149.1 compliant) interface, including boundary scan

 PDI (program and debug interface)

 I/O and packages

 50 Programmable I/O pins

 64-lead TQFP

 64-pad QFN

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA A3U Microcontroller

ATxmega256A3U / ATxmega192A3U /

ATxmega128A3U / ATxmega64A3U

Summary of content (331 pages)

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8/16-bit Atmel XMEGA A3U Microcontroller ATxmega256A3U / ATxmega192A3U / ATxmega128A3U / ATxmega64A3U Features        High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller Nonvolatile program and data memories  64K - 256KBytes of in-system self-programmable flash  4K - 8KBytes boot section  2K - 4KBytes EEPROM  4K - 16KBytes internal SRAM Peripheral features  Four-channel DMA controller  Eight-channel event system  Seven 16-bit timer/counters  Four timer/counters with
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1.
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2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout. Programming, debug, test Power Ground External clock /Crystal pins General Purpose I /O PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI PF7 PF6 VCC GND PF5 PF4 PF3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Digital function Analog function /Oscillators Port R PC0 16 Note: 1.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block Diagram Figure 3-1. XMEGA A3U block diagram. PR[0..1] Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock XTAL1 General Purpose I/O XTAL2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter DATA BUS PA[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  Atmel AVR XMEGA AU manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU manual describes the modules and peripherals in depth.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   142 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. 7. Memories 7.
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7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.
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7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
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Table 7-3. Byte Address Data memory map (Hexadecimal address). ATxmega192A3U 0 FFF I/O Registers (4K) 1000 EEPROM (2K) 17FF Byte Address ATxmega128A3U 0 FFF 1000 17FF RESERVED 2000 Internal SRAM (16K) 5FFF Byte Address I/O Registers (4K) EEPROM (2K) Byte Address 0 FFF 1000 17FF RESERVED 2000 3FFF Internal SRAM (8K) ATxmega64A3U I/O Registers (4K) EEPROM (2K) RESERVED 2000 2FFF Internal SRAM (4K) ATxmega256A3U 0 FFF 1000 13FF I/O Registers (4K) EEPROM (4K) RESERVED 2000 27FF 7.
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7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle.
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Table 7-5. Devices Number of bytes and pages in the EEPROM.
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8. DMAC – Direct Memory Access Controller 8.
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9. Event System 9.
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Figure 9-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network ADC AC clkPER Prescaler Real Time Counter Event System Controller Timer / Counters DAC USB Port pins IRCOM The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event routing configurations.
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10. System Clock and Clock options 10.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators: 32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output    External clock options 0.4MHz - 16MHz crystal oscillator 32.
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Figure 10-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB System Clock Prescalers Brown-out Detector Prescaler Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32kHz Int. ULP 32.768kHz Int. OSC 32.768kHz TOSC 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 10.3 0.
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency.
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11. Power Management and Sleep Modes 11.1 Features  Power management for adjusting power consumption and functions  Five sleep modes Idle Power down  Power save  Standby  Extended standby    Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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11.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 11.3.
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12. System Control and Reset 12.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 12.
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12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin.
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13. WDT – Watchdog Timer 13.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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14. Interrupts and Programmable Multilevel Interrupt Controller 14.
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Program address (base address) Source Interrupt description 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x038 USARTC1_INT_base USART 1 on port C Interrupt base 0x03E AES_INT_vect AES Interrupt vector 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x048 ACB_INT_base Analog Comparator on Port B Interrupt base 0x
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15. I/O Ports 15.
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15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
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15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Figure 15-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R NVERTED I/O Asynchronou Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.
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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 16.
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Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers.
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17. TC2 - Timer/Counter Type 2 17.
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18. AWeX – Advanced Waveform Extension 18.
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19. Hi-Res – High Resolution Extension 19.1 Features  Increases waveform generator resolution up to 8x (three bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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20. RTC – 16-bit Real-Time Counter 20.1 Features  16-bit resolution  Selectable clock source 32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator    Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 20.
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21. USB – Universal Serial Bus Interface 21.1 Features  One USB 2.0 full speed (12Mbps) and low speed (1.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB.
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22. TWI – Two-Wire Interface 22.
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23. SPI – Serial Peripheral Interface 23.1 Features  Three Identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 23.
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24. USART 24.
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25. IRCOM – IR Communication Module 25.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2Kbps  Selectable pulse modulation scheme 3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled    Built-in filtering  Can be connected to and used by any USART 25.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
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27. CRC – Cyclic Redundancy Check Generator 27.
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28. ADC – 12-bit Analog to Digital Converter 28.1 Features  Two Analog to Digital Converters (ADCs)  12-bit resolution  Up to two million samples per second Two inputs can be sampled simultaneously using ADC and 1x gain stage Four inputs can be sampled within 1.5µs  Down to 2.5µs conversion time with 8-bit resolution  Down to 3.
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Figure 28-1. ADC overview. ADC0 Compare • •• ADC11 ADC0 Internal signals VINP CH0 Result •• • CH1 Result ADC7 ADC4 Threshold (Int Req) ½x - 64x CH2 Result • •• ADC7 Int. signals < > Internal signals CH3 Result VINN ADC0 • •• ADC3 Int. signals Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting.
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29. DAC – 12-bit Digital to Analog Converter 29.
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The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or ADC. PORTB has one DAC. Notation of this peripheral is DACB.
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30. AC – Analog Comparator 30.
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Figure 30-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis DAC Voltage Scaler Enable ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Figure 30-2. Analog comparator window function.
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31. Programming and Debugging 31.
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32. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 32.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 32.1.
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TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB 32.1.6 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 32.1.
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32.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 32-1. Port A - alternate functions.
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Table 32-3. Port C - alternate functions. PORTC PIN# INTERRUPT TCC0 AWEXC TCC1 (1)(2) USART C0 (3) USART C1 TWIC TWIC w/ext driver SDA SDAIN SCL SCLIN SPIC (4) PC0 16 SYNC OC0A OC0ALS PC1 17 SYNC OC0B OC0AHS XCK0 PC2 18 SYNC/ ASYNC OC0C OC0BLS RXD0 SDAOUT PC3 19 SYNC OC0D OC0BHS TXD0 SCLOUT PC4 20 SYNC OC0CLS OC1A PC5 21 SYNC OC0CHS OC1B PC6 22 SYNC PC7 23 SYNC GND 24 VCC 25 Notes: 1. 2. 3. 4. 5. 6.
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Table 32-5. Port E - alternate functions. PORTE USART E1 SPIE SDA SDAIN SCL SCLIN TCE0 PE0 36 SYNC OC0A PE1 37 SYNC OC0B XCK0 PE2 38 SYNC/ASYNC OC0C RXD0 SDAOUT PE3 39 SYNC OC0D TXD0 SCLOUT PE4 40 SYNC OC1A PE5 41 SYNC OC1B PE6 42 PE7 43 GND 44 VCC 45 1. 2. 3. 4. 5. 6.
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33. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A3U. For complete register description and summary for each peripheral module, refer to the XMEGA AU manual. Table 33-1. Peripheral module address map.
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Base address Name Description 0x04A0 TWIE Two Wire Interface on port E 0x04C0 USB Universal Serial Bus Interface 0x0600 PORTA Port A 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08
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34.
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Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3 (1) call Subroutine PC  k None 3 / 4 (1) RET Subroutine Return PC  STACK None 4 / 5 (1) RETI Interrupt Return PC  STACK I 4 / 5 (1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with
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Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd  (k) None 2 (1)(2) LD Rd, X Load Indirect Rd  (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y+1 None 1 (1)(2) LD Rd, -Y Load In
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Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1 (1) Pop Register from Stack Rd  STACK None 2 (1) Z, Rd Exchange RAM location Temp Rd (Z)    Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z)    Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp R
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Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr.
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35. Packaging information 35.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 SYMBOL Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A2 0.95 1.
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35.2 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1.
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36. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. Note: 36.1 For devices that are not available yet, preliminary values in this datasheet are based on simulations, and/or characterization of similar AVR XMEGA microcontrollers.
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Table 36-3. Operating voltage and frequency. Symbol Parameter ClkCPU CPU clock frequency Condition Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 36-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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36.1.3 Current consumption Table 36-4. Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T = 85°C Power-save power consumption (2) Reset power consumption Notes: 1. 2.
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Table 36-5. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 26 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog Timer ICC Typ.
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36.1.4 Wake-up time from sleep modes Table 36-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Condition External 2MHz clock Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. 32.768kHz internal oscillator Min. Typ. (1) Max. Units 2 120 2MHz internal oscillator 2 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.
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36.1.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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36.1.6 ADC characteristics Table 36-8. Symbol Power supply, reference and input range. Parameter AVCC Analog supply voltage VREF Reference voltage Rin Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Input resistance Switched 5.0 k Csample Input capacitance Switched 5.
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Table 36-10. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset Error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
PAGE 75
Symbol Parameter Condition Offset Error, input referred Min. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.1.7 DAC Characteristics Table 36-12. Power supply, reference and output range.
PAGE 76
Table 36-14. Accuracy characteristics. Symbol RES Parameter Condition Min. Input Resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
PAGE 77
Symbol tdelay Parameter Propagation delay Condition VCC = 3.0V, T= 85°C mode = HS Typ. Max. 60 90 Units ns 30 VCC = 1.6V - 3.6V mode = LP 64-Level Voltage Scaler Min. 160 Integral non-linearity (INL) 0.3 0.5 lsb 36.1.9 Bandgap and Internal 1.0V Reference Characteristics Table 36-16. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC or DAC Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.
PAGE 78
36.1.11 External Reset Characteristics Table 36-18. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.70*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.30*VCC Reset pin Pull-up Resistor V 25 k 36.1.12 Power-on Reset Characteristics Table 36-19. Power-on reset characteristics.
PAGE 79
Table 36-21. Programming time. Symbol Parameter Condition Chip Erase 64KB Flash, EEPROM (2) Application Erase Flash EEPROM Notes: 1. 2. Min. and SRAM Erase Typ. (1) Max. Units 55 ms Section erase 6 ms Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 ms ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 36.1.
PAGE 80
36.1.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 36-24. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. Units 55 MHz 32 T = 85C, VCC= 3.0V User calibration accuracy MHz -1.5 1.5 % -0.2 0.2 % DFLL calibration step size 0.23 % 36.1.14.
PAGE 81
36.1.14.6 External clock characteristics Figure 36-3. External clock drive waveform tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 36-27. External clock used as system clock without prescaling. Symbol Clock Frequency (1) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.
PAGE 82
Table 36-28. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
PAGE 83
Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
PAGE 84
36.1.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-30. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.
PAGE 85
36.1.15 SPI Characteristics Figure 36-5. SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 36-6. SPI timing requirements in slave mode.
PAGE 86
Table 36-31. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.
PAGE 87
36.1.16 Two-Wire Interface Characteristics Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 367. Figure 36-7. Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 36-32. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol Parameter tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.7 fSCL > 100kHz 0.6 fSCL  100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.
PAGE 89
36.2 ATxmega128A3U 36.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-33. Absolute maximum ratings. Symbol Parameter Condition Min. Typ.
PAGE 90
Figure 36-8. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
PAGE 91
36.2.3 Current consumption Table 36-36. Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T = 85°C Power-save power consumption (2) Reset power consumption Notes: 1. 2.
PAGE 92
Table 36-37. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 27 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog Timer ICC Typ.
PAGE 93
36.2.4 Wake-up time from sleep modes Table 36-38. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Condition External 2MHz clock Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. 32.768kHz internal oscillator Min. Typ. (1) Max. Units 2 120 2MHz internal oscillator 2 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.
PAGE 94
36.2.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-39. I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.2*VCC VCC = 1.6 - 2.0V -0.3 0.
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36.2.6 ADC characteristics Table 36-40. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Rin Input resistance Switched 5.0 k Csample Input capacitance Switched 5.
PAGE 96
Table 36-42. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset Error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
PAGE 97
Symbol Parameter Condition Offset Error, input referred Min. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.2.7 DAC Characteristics Table 36-44. Power supply, reference and output range.
PAGE 98
Table 36-46. Accuracy characteristics. Symbol RES Parameter Condition Min. Input Resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
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Symbol tdelay Parameter Propagation delay Condition mode = HS mode = LP 64-Level Voltage Scaler Min. VCC = 3.0V, T= 85°C Typ. Max. 90 100 95 VCC = 1.6V - 3.6V Integral non-linearity (INL) Units ns 200 500 0.5 1.0 lsb 36.2.9 Bandgap and Internal 1.0V Reference Characteristics Table 36-48. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC or DAC Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.
PAGE 100
36.2.11 External Reset Characteristics Table 36-50. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST VCC = 3.0 - 3.6V 0.50*VCC VCC = 2.3 - 2.7V 0.40*VCC VCC = 3.0 - 3.6V 0.50*VCC VCC = 2.3 - 2.7V 0.40*VCC Reset pin Pull-up Resistor V 25 k 36.2.12 Power-on Reset Characteristics Table 36-51. Power-on reset characteristics.
PAGE 101
Table 36-53. Programming time. Symbol Parameter Chip Erase 128KB Flash, EEPROM Application Erase Flash EEPROM Notes: 1. 2. Condition (2) Min. and SRAM Erase Typ. (1) Max. Units 75 ms Section erase 6 ms Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 ms ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 36.2.
PAGE 102
36.2.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 36-56. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. Units 55 MHz 32 T = 85C, VCC= 3.0V User calibration accuracy MHz -1.5 1.5 % -0.2 0.2 % DFLL calibration step size 0.23 % 36.2.14.
PAGE 103
36.2.14.6 External clock characteristics Figure 36-10.External clock drive waveform tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 36-59. External clock used as system clock without prescaling. Symbol Clock Frequency (1) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.
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Table 36-60. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
PAGE 106
36.2.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-62. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.
PAGE 107
36.2.15 SPI Characteristics Figure 36-12.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 36-13.SPI timing requirements in slave mode.
PAGE 108
Table 36-63. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.
PAGE 109
36.2.16 Two-Wire Interface Characteristics Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 367. Figure 36-14.Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 36-64. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
PAGE 110
Symbol Parameter tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.7 fSCL > 100kHz 0.6 fSCL  100kHz 0 3.5 fSCL > 100kHz 0 0.9 fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.
PAGE 111
36.3 ATxmega192A3U 36.3.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-65. Absolute maximum ratings. Symbol Parameter Condition Min. Typ.
PAGE 112
Figure 36-15.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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36.3.3 Current consumption Table 36-68. Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T = 85°C Power-save power consumption (2) Reset power consumption Notes: 1. 2.
PAGE 114
Table 36-69. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 27 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog Timer ICC Typ.
PAGE 115
36.3.4 Wake-up time from sleep modes Table 36-70. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Condition External 2MHz clock Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. 32.768kHz internal oscillator Min. Typ. (1) Max. Units 2 120 2MHz internal oscillator 2 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.
PAGE 116
36.3.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-71. I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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36.3.6 ADC characteristics Table 36-72. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Rin Input resistance Switched 4.0 k Csample Input capacitance Switched 4.
PAGE 118
Table 36-74. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset Error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
PAGE 119
Symbol Parameter Condition Offset Error, input referred Min. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.3.7 DAC Characteristics Table 36-76. Power supply, reference and output range.
PAGE 120
Table 36-78. Accuracy characteristics. Symbol RES Parameter Condition Min. Input Resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
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Symbol Parameter Condition VCC = 3.0V, T= 85°C tdelay Propagation delay Min. mode = HS mode = HS VCC = 3.0V, T= 85°C Max. 30 90 30 mode = LP 130 mode = LP 64-Level Voltage Scaler Typ. 500 Units ns 130 Integral non-linearity (INL) 0.3 0.5 lsb 36.3.9 Bandgap and Internal 1.0V Reference Characteristics Table 36-80. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC or DAC Max. 1 ClkPER + 2.
PAGE 122
36.3.11 External Reset Characteristics Table 36-82. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.70*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.30*VCC Reset pin Pull-up Resistor V 25 k 36.3.12 Power-on Reset Characteristics Table 36-83. Power-on reset characteristics.
PAGE 123
Table 36-85. Programming time. Symbol Parameter Chip Erase 192KB Flash, EEPROM Application Erase Flash EEPROM Notes: 1. 2. Condition (2) Min. and SRAM Erase Typ. (1) Max. Units 90 ms Section erase 6 ms Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 ms ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 36.3.
PAGE 124
36.3.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 36-88. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. Units 55 MHz 32 T = 85C, VCC= 3.0V User calibration accuracy MHz -1.5 1.5 % -0.2 0.2 % DFLL calibration step size 0.23 % 36.3.14.
PAGE 125
36.3.14.6 External clock characteristics Figure 36-17.External clock drive waveform tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 36-91. External clock used as system clock without prescaling. Symbol Clock Frequency (1) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.
PAGE 126
Table 36-92. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
PAGE 128
36.3.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-94. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.
PAGE 129
36.3.15 SPI Characteristics Figure 36-19.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 36-20.SPI timing requirements in slave mode.
PAGE 130
Table 36-95. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
PAGE 131
36.3.16 Two-Wire Interface Characteristics Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 367. Figure 36-21.Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 36-96. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol Parameter tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.7 fSCL > 100kHz 0.6 fSCL  100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.
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36.4 ATxmega256A3U 36.4.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-97. Absolute maximum ratings. Symbol Parameter Condition Min. Typ.
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Figure 36-22.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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36.4.3 Current consumption Table 36-100.Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T = 85°C Power-save power consumption (2) Reset power consumption Notes: 1. 2.
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Table 36-101.Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 27 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog Timer ICC Typ.
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36.4.4 Wake-up time from sleep modes Table 36-102.Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Condition External 2MHz clock Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. 32.768kHz internal oscillator Min. Typ. (1) Max. Units 2 120 2MHz internal oscillator 2 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.
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36.4.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-103.I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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36.4.6 ADC characteristics Table 36-104. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Rin Input resistance Switched 4.0 k Csample Input capacitance Switched 4.
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Table 36-106.Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset Error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
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Symbol Parameter Condition Offset Error, input referred Min. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.4.7 DAC Characteristics Table 36-108.Power supply, reference and output range.
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Table 36-110.Accuracy characteristics. Symbol RES Parameter Condition Min. Input Resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Units 12 Bits ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.
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Symbol Parameter Condition VCC = 3.0V, T= 85°C tdelay Propagation delay Min. mode = HS mode = HS VCC = 3.0V, T= 85°C Max. 30 90 30 mode = LP 130 mode = LP 64-Level Voltage Scaler Typ. 500 Units ns 130 Integral non-linearity (INL) 0.3 0.5 lsb 36.4.9 Bandgap and Internal 1.0V Reference Characteristics Table 36-112. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC or DAC Max. 1 ClkPER + 2.
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36.4.11 External Reset Characteristics Table 36-114.External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.70*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.30*VCC Reset pin Pull-up Resistor V 25 k 36.4.12 Power-on Reset Characteristics Table 36-115.Power-on reset characteristics.
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Table 36-117.Programming time. Symbol Parameter Chip Erase 256KB Flash, EEPROM Application Erase Flash EEPROM Notes: 1. 2. Condition (2) Min. and SRAM Erase Typ. (1) Max. Units 105 ms Section erase 6 ms Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 ms ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 36.4.
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36.4.14.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 36-120. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. Units 55 MHz 32 T = 85C, VCC= 3.0V User calibration accuracy MHz -1.5 1.5 % -0.2 0.2 % DFLL calibration step size 0.23 % 36.4.14.
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36.4.14.6 External clock characteristics Figure 36-24.External clock drive waveform tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 36-123.External clock used as system clock without prescaling. Symbol Clock Frequency (1) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.
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Table 36-124.External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
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36.4.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-126.External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin 4.2 pF CTOSC2 Parasitic capacitance TOSC2 pin 4.3 pF Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.
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36.4.15 SPI Characteristics Figure 36-26.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 36-27.SPI timing requirements in slave mode.
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Table 36-127.SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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36.4.16 Two-Wire Interface Characteristics Table 36-32 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 367. Figure 36-28.Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 36-128.Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol Parameter tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.7 fSCL > 100kHz 0.6 fSCL  100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.
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37. Typical Characteristics 37.1 ATxmega64A3U 37.1.1 Current consumption 37.1.1.1 Active mode supply current Figure 37-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 700 3.6 V 600 3.0 V 500 ICC [µA] 2.7 V 400 2.2 V 300 1.8 V 1.6 V 200 100 0 0 0.2 0.4 0.6 0.8 1 Frequency [MHz] Figure 37-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.6 V 12 ICC [mA] 10 3.0 V 2.7 V 8 6 2.2 V 4 2 1.8 V 1.
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Figure 37-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 250 -40°C 230 210 25°C 85°C ICC [µA] 190 170 150 130 110 90 70 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 760 -40°C 25°C 85°C 690 620 ICC [µA] 550 480 410 340 270 200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1525 -40°C 25°C 85°C 1400 1275 ICC [µA] 1150 1025 900 775 650 525 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.9 -40°C 25°C 85°C 5.4 4.9 ICC [mA] 4.4 3.9 3.4 2.9 2.4 1.9 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 14 -40°C 13 25°C 85°C ICC [mA] 12 11 10 9 8 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.1.1.2 Idle mode supply current Figure 37-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.6 V ICC [µA] 160 140 3.0 V 120 2.7 V 100 2.2 V 80 1.8 V 1.6 V 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 37-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.6 V 5 3.0 V ICC [mA] 4 2.7 V 3 2.2 V 2 1 1.8 V 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-10. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. ICC [µA] 34 33 -40°C 85°C 32 25°C 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-11. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 180 85°C 25°C -40°C 165 150 ICC [µA] 135 120 105 90 75 60 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-12. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 460 -40°C 25°C 85°C 420 ICC [µA] 380 340 300 260 220 180 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-13. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.3 -40°C 25°C 85°C 2.1 ICC [mA] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-14. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 14 -40°C 13 25°C 85°C ICC [mA] 12 11 10 9 8 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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37.1.1.3 Power-down mode supply current Figure 37-15. Power-down mode supply current vs. VCC. All functions disabled. 1.5 85°C ICC [µA] 1.2 0.9 0.6 0.3 25°C -40°C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-16. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 2.8 85°C 2.6 2.4 ICC [µA] 2.2 2.0 1.8 1.6 25°C -40°C 1.4 1.2 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.1.1.4 Power-save mode supply current Figure 37-17. Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal Mode 0.80 Icc [µA] 0.75 0.70 Low-Power Mode 0.65 0.60 0.55 0.50 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Vcc [V] 37.1.1.5 Standby mode supply current Figure 37-18. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 7.5 ICC [µA] 7.0 6.5 6.0 5.5 5.0 4.5 4.
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Figure 37-19. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 440 12MHz 400 Icc [µA] 360 8MHz 320 280 2MHz 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] 37.1.2 I/O Pin Characteristics 37.1.2.1 Pull-up Figure 37-20. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 Ipin [µA] 48 40 32 24 16 -40°C 25°C 85°C 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.
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Figure 37-21. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 Ipin [µA] 75 60 45 30 -40°C 25°C 85°C 15 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 VPIN [V] Figure 37-22. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 Ipin [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.
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37.1.2.2 Output Voltage vs. Sink/Source Current Figure 37-23. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 -40°C 25°C 0.9 85°C 0.7 0.5 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 37-24. I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.9 2.6 VPIN [V] 2.3 2.0 1.7 1.4 1.1 -40°C 0.8 25°C 85°C 0.
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Figure 37-25. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.2 2.9 VPIN [V] 2.6 2.3 2.0 -40°C 1.7 1.4 25°C 1.1 0.8 85°C 0.5 -30 -25 -20 -15 -10 -5 0 IPIN [mA] Figure 37-26. I/O pin output voltage vs. source current. 3.7 3.6 V 3.3 3.3 V 3.0 V 2.9 2.7 V VPIN [V] 2.5 2.1 1.8 V 1.6 V 1.7 1.3 0.9 0.
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Figure 37-27. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 85°C 0.8 25°C VPIN [V] 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-28. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.
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Figure 37-29. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] Figure 37-30. I/O pin output voltage vs. sink current. 1.5 1.8 V 1.6 V 1.4 1.2 VPIN [V] 1.1 2.7 V 3.0 V 3.3 V 3.6 V 0.9 0.8 0.6 0.5 0.3 0.2 0.
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37.1.2.3 Thresholds and Hysteresis Figure 37-31. I/O pin input threshold voltage vs. VCC. T = 25°C. VTHRESHOLD [V] 1.85 1.70 VIH 1.55 VIL 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-32. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 25°C 85°C 1.7 VTHRESHOLD [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-33. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.70 -40°C 25°C 85°C 1.55 VTHRESHOLD [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-34. I/O pin input hysteresis vs. VCC. 0.36 0.33 VTHRESHOLD [V] 0.3 -40°C 0.27 25°C 0.24 0.21 0.18 85°C 0.15 0.12 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.1.3 ADC Characteristics Figure 37-35. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 3.0 Single-ended unsigned mode 2.5 INL[LSB] 2.0 1.5 Single-ended signed mode 1.0 Dif f erential mode 0.5 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-36. INL error vs. sample rate. T = 25C, VCC = 2.7V, VREF = 1.0V external. 2.0 1.8 Single-ended unsigned mode 1.6 INL[LSB] 1.4 1.2 Single-ended signed mode 1.0 0.8 Dif f erential mode 0.6 0.
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Figure 37-37. INL error vs. input code. 2.0 1.5 1.0 INL [LSB] 0.5 0.0 -0.5 -0.1 -1.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 37-38. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.1 1.0 Single_ended unsigned mode 0.9 DNL [LSB] 0.8 0.7 0.6 Single-ended signed mode 0.5 0.4 Dif f erential mode 0.3 0.2 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-39. DNL error vs. sample rate. T = 25C, VCC = 2.7V, VREF = 1.0V external. 0.5 0.5 Single-ended unsigned mode DNL [LSB] 0.4 Dif f erential mode 0.4 0.3 Single-ended signed mode 0.3 0.2 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sample rate [ksps] Figure 37-40. DNL error vs. input code. 1.0 0.8 0.6 0.4 DNL [LSB] 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.
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Figure 37-41. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 10 9 Single-ended signed mode 8 Gain Error [mV] 7 Single-ended unsigned mode 6 5 4 3 Dif f erential mode 2 1 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 30 Vref [V] Figure 37-42. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.7 Single-ended signed mode 0.6 Noise [mV RMS] 0.5 Single-ended unsigned mode 0.4 0.3 Dif f erential mode 0.2 0.1 0.0 1.6 1.8 2.0 2.
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Figure 37-43. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -0.80 -0.85 Offset Error [mV] -0.90 -0.95 -1.00 Dif f erential mode -1.05 -1.10 -1.15 -1.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-44. Gain error vs. temperature. VCC = 2.7V, VREF = external 1.0V.
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Figure 37-45. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.2 Offset Error [mV] 0.0 -0.2 Dif f erential mode -0.4 -0.6 -0.8 -1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] Figure 37-46. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.9 Single-ended signed mode 0.8 Noise [mV RMS] 0.7 0.6 Single-ended unsigned mode 0.5 0.4 0.3 Dif f erential mode 0.2 0.1 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-47. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.7 Single-ended signed mode 0.6 Noise [mV RMS] 0.5 Single-ended unsigned mode 0.4 0.3 Dif f erential mode 0.2 0.1 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] 37.1.4 DAC Characteristics Figure 37-48. DAC INL error vs. VREF. VCC = 3.6V. 2.3 2.1 DAC INL [LSB] 1.9 1.7 1.5 1.3 1.1 -40°C 0.9 25°C 85°C 0.7 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-49. DNL error vs. VREF. T = 25C, VCC = 3.6V. 1.6 1.4 DAC DNL [LSB] 1.2 1.0 0.8 -40°C 25°C 85°C 0.6 0.4 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-50. DAC noise vs. temperature. VCC = 3.3V, VREF = 2.0V . 0.200 Noise[mV RMS] 0.195 0.190 0.185 0.180 0.175 0.
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37.1.5 Analog Comparator Characteristics Figure 37-51. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 13 12 85°C VHYST [mV] 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-52. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 27 85°C 26 25 VHYST [mV] 24 25°C 23 22 21 -40°C 20 19 18 17 16 15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-53. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 45 85°C 43 25°C 41 VHYST [mV] 39 -40°C 37 35 33 31 29 27 1.6 2.1 2.6 3.1 3.6 VCC [V] Figure 37-54. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 73 85°C 70 67 VHYST [mV] 64 25°C 61 58 -40°C 55 52 49 46 1.6 2.1 2.6 3.1 3.
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Figure 37-55. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 ICURRENTSOURCE [µA] 7 6 5 3.6 V 4 3.0 V 2.7 V 3 2.2 V 1.8 V 1.6 V 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 37-56. Analog comparator current source vs. calibration value. VCC = 3.0V. 6.7 ICURRENTSOURCE [µA] 6.3 5.9 5.5 5.1 4.7 4.3 -40°C 25°C 85°C 3.9 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
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Figure 37-57. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.06 0.05 0.04 INL [LSB] 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 0 8 16 24 32 40 48 56 64 SCALEFAC 37.1.6 Internal 1.0V reference Characteristics Figure 37-58. ADC/DAC Internal 1.0V reference vs. temperature. 1.011 Bandgap Voltage [V] 1.010 1.008 1.007 1.005 1.004 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 1.002 1.001 0.
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37.1.7 BOD Characteristics Figure 37-59. BOD thresholds vs. temperature. BOD level = 1.6V. 1.653 1.650 1.647 VBOT [V] 1.644 Rising Vcc 1.641 1.638 1.635 1.632 Falling Vcc 1.629 1.626 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 75 85 Temperature [°C] Figure 37-60. BOD thresholds vs. temperature. BOD level = 3.0V. 3.08 3.07 Rising Vcc VBOT [V] 3.06 3.05 3.04 3.03 Falling Vcc 3.02 3.
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37.1.8 External Reset Characteristics Figure 37-61. Minimum Reset pin pulse width vs. VCC. 135 130 125 tRST [ns] 120 115 110 105 100 85°C 95 25°C -40°C 90 85 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-62. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 72 64 56 IRESET [µA] 48 40 32 24 16 -40°C 8 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 37-63. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 120 105 IRESET [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 37-64. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 135 120 105 IRESET [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 37-65. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.20 -40°C 2.05 25°C 85°C VTHRESHOLD [V] 1.90 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-66. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.1.9 Power-on Reset Characteristics Figure 37-67. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 600 -40°C 25°C 85°C 525 ICC [µA] 450 375 300 225 150 75 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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37.1.10 Oscillator Characteristics 37.1.10.1 Ultra Low-Power internal oscillator Figure 37-68. Ultra Low-Power internal oscillator frequency vs. temperature. 34.3 34.0 Frequency [kHz] 33.7 33.4 33.1 32.8 32.5 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.2 31.9 31.6 31.3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 37.1.10.2 32.768kHz Internal Oscillator Figure 37-69. 32.768kHz internal oscillator frequency vs. temperature. 32.8 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.
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Figure 37-70. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 49 46 Frequency [kHz] 43 40 37 34 31 28 25 22 0 26 52 78 104 130 156 182 208 234 260 RC32KCAL[7..0] 37.1.10.3 2MHz Internal Oscillator Figure 37-71. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.02 2.00 1.
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Figure 37-72. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.005 2.7 V 2.2 V 1.8 V 2.000 Frequency [MHz] 1.995 1.990 1.985 1.980 1.6 V 1.975 1.970 1.965 3.6 V 3.0 V 1.960 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-73. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.33 % Frequency Step size [%] 0.31 % 0.29 % 0.27 % 0.25 % 0.23 % 0.21 % 0.19 % 25°C 0.17 % -40°C 0.
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37.1.10.4 32MHz Internal Oscillator Figure 37-74. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.0 35.5 Frequency [MHz] 35.0 34.5 34.0 33.5 33.0 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-75. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.05 3.6 V 31.95 3.0 V 2.7 V 1.8 V 1.6 V Frequency [MHz] 31.85 31.75 31.65 31.55 31.
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Figure 37-76. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.48 % Frequency Step Size [%] 0.43 % 0.38 % 0.33 % 0.28 % 0.23 % -40°C 0.18 % 85°C 25°C 0.13 % 0.08 % 0 16 32 48 64 80 96 112 128 CALA Figure 37-77. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V. 2.80 % Frequency Step size [%] 2.60 % 2.40 % 2.20 % 2.00 % 1.80 % 1.60 % 1.40 % 1.20 % -40°C 85°C 25°C 1.00 % 0.
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37.1.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-78. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53.6 52.8 Frequency [MHz] 52.0 51.2 50.4 49.6 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 48.8 48.0 47.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-79. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.100 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 47.950 Frequency [MHz] 47.
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Figure 37-80. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.36 % Frequency Step size [%] 0.33 % 0.30 % 0.27 % 0.24 % 0.21 % -40°C 0.18 % 25°C 85°C 0.15 % 0.12 % 0 16 32 48 64 80 96 112 128 CALA 37.1.11 Two-Wire Interface characteristics Figure 37-81. SDA hold time vs. temperature.
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Figure 37-82. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.1.12 PDI characteristics Figure 37-83. Maximum PDI frequency vs. VCC. 42 -40°C Maximum Frequency [MHz] 38 25°C 34 85°C 30 26 22 18 14 10 1.6 2.1 2.6 3.1 3.
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37.2 ATxmega128A3U 37.2.1 Current consumption 37.2.1.1 Active mode supply current Figure 37-84. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 1000 3.6 V 900 ICC [µA] 800 700 3.0 V 600 2.7 V 500 2.2 V 400 1.8 V 1.6 V 300 200 100 0 0 0.2 0.4 0.6 0.8 1 Frequency [MHz] Figure 37-85. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.6 V 12 3.0 V ICC [mA] 10 2.7 V 8 6 2.2 V 4 1.8 V 1.
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Figure 37-86. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 460 -40°C 420 380 25°C ICC [µA] 340 85°C 300 260 220 180 140 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-87. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 980 -40°C 900 25°C 85°C 820 ICC [µA] 740 660 580 500 420 340 260 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-88. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1750 -40°C 1625 25°C 85°C 1500 ICC [µA] 1375 1250 1125 1000 875 750 625 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-89. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 6.0 -40°C 25°C 85°C 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-90. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 15.3 -40°C 14.6 25°C 13.9 85°C ICC [mA] 13.2 12.5 11.8 11.1 10.4 9.7 9.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.2.1.2 Idle mode supply current Figure 37-91. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.6 V 150 ICC [µA] 3.0 V 120 2.7 V 90 2.2 V 1.8 V 1.6 V 60 30 0 0 0.2 0.4 0.6 0.
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Figure 37-92. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.6 V 5 3.0 V ICC [mA] 4 2.7 V 3 2.2 V 2 1 1.8 V 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-93. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. ICC [µA] 34 33 -40°C 85°C 32 25°C 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-94. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 180 85°C 25°C -40°C 165 150 ICC [µA] 135 120 105 90 75 60 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-95. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 450 -40°C 25°C 85°C 420 390 ICC [µA] 360 330 300 270 240 210 180 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-96. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 23 21 -40°C 25°C 85°C ICC [mA] 19 17 15 13 11 9 7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-97. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. ICC [mA] 63 60 -40°C 57 25°C 85°C 54 51 48 45 42 39 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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37.2.1.3 Power-down mode supply current Figure 37-98. Power-down mode supply current vs. VCC. All functions disabled. 1.6 85°C 1.4 1.2 ICC [µA] 1 0.8 0.6 0.4 0.2 25°C -40°C 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-99. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 2.8 85°C 2.6 2.4 ICC [µA] 2.2 2 1.8 1.6 -40°C 25°C 1.4 1.2 1 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.2.1.4 Power-save mode supply current Figure 37-100. Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.2.1.5 Standby mode supply current Figure 37-101. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 7.5 ICC [µA] 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.
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Figure 37-102. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.2.2 I/O Pin Characteristics 37.2.2.1 Pull-up Figure 37-103. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 IPIN [µA] 48 40 32 24 -40°C 25°C 85°C 16 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 37-104. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 IPIN [µA] 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 37-105. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 120 IPIN [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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37.2.2.2 Output Voltage vs. Sink/Source Current Figure 37-106. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.9 1.7 VPIN [V] 1.6 1.4 1.3 1.1 -40°C 1.0 25°C 0.8 85°C 0.7 0.5 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 37-107. I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.9 2.6 VPIN [V] 2.3 2.0 1.7 -40°C 1.4 1.1 25°C 85°C 0.8 0.
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Figure 37-108. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.2 2.9 VPIN [V] 2.6 2.3 2.0 -40°C 1.7 1.4 85°C 1.1 0.8 25°C 0.5 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 37-109. I/O pin output voltage vs. source current. VPIN [V] 4.0 3.5 3.6 V 3.0 3.0 V 2.7 V 2.5 2.0 1.8 V 1.6 V 1.5 1.
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Figure 37-110. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 85°C VPIN [V] 0.8 0.7 25°C 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 37-111. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85°C 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.
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Figure 37-112. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] Figure 37-113. I/O pin output voltage vs. sink current. 1.50 1.6 V 1.8 V 1.35 1.20 VPIN [V] 1.05 2.7 V 3.0 V 3.3 V 3.6 V 0.90 0.75 0.60 0.45 0.30 0.15 0.
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37.2.2.3 Thresholds and Hysteresis Figure 37-114. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.70 VIH 1.55 VIL VTHRESHOLD [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-115. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 1.7 25°C 85°C VTHRESHOLD [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-116. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.70 85°C 25°C -40°C 1.55 VTHRESHOLD [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-117. I/O pin input hysteresis vs. VCC. 0.36 0.33 0.30 VHYST [V] -40°C 0.27 25°C 0.24 0.21 0.18 0.15 85°C 0.12 1.6 1.8 2 2.2 2.4 2.
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37.2.3 ADC Characteristics Figure 37-118. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 3.0 Single-ended unsigned mode 2.5 INL [LSB] 2.0 Dif f erential mode 1.5 1.0 Single-ended signed mode 0.5 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-119. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 3 Single-ended unsigned mode 2.5 INL[LSB] 2 1.5 Dif f erential mode 1 Single-ended signed mode 0.
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Figure 37-120. INL error vs. input code. 2.0 1.5 1.0 INL [LSB] 0.5 0.0 -0.5 -0.1 -1.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 37-121. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.15 1.05 Single-ended unsigned mode 0.95 DNL [LSB] 0.85 0.75 Dif f erential mode 0.65 0.55 Single-ended signed mode 0.45 0.35 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-122. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 1.00 0.95 Single-ended unsigned mode 0.90 0.85 DNL [LSB] Dif f erential mode 0.80 0.75 0.70 0.65 Single-ended signed mode 0.60 0.55 0.50 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sampling rate [kSps] Figure 37-123. DNL error vs. input code. 1.0 0.8 0.6 0.4 DNL [LSB] 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.
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Figure 37-124. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 3 Single-ended signed mode 2 Gain Error [mV] 1 Single-ended unsigned mode 0 -1 -2 -3 Dif f erential mode -4 -5 1.0 1.2 1.4 1.6 1.8 2.0 Vref [V] 2.2 2.4 2.6 2.8 3.0 Figure 37-125. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.5 Gain Error [mV] 1.0 Single-ended signed mode 0.5 0.0 -0.5 Single-ended unsigned mode -1.0 Dif f erential mode -1.5 1.6 1.8 2.
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Figure 37-126. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.1 Offset[mV] -1.2 -1.3 Dif f erential mode -1.4 -1.5 -1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref[V] Figure 37-127. Gain error vs. temperature. VCC = 2.7V, VREF = external 1.0V.
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Figure 37-128. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.2 Offset Error [mV] -0.4 -0.6 Dif f erential mode -0.8 -1.0 -1.2 -1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 Vcc [V] Figure 37-129. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.6 Single-ended unsigned mode 0.6 Noise [mV RMS] 0.5 0.5 Single-ended signed mode 0.4 0.4 Dif f erential mode 0.3 0.3 0.2 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 37-130. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.6 Single-ended unsigned mode 0.6 Noise [mV RMS] 0.5 0.5 0.4 Single-ended signed mode 0.4 0.3 Dif f erential signed 0.3 0.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] 37.2.4 DAC Characteristics Figure 37-131. DAC INL error vs. VREF. VCC = 3.6V. 2.7 2.5 2.3 INL [LSB] 2.1 1.9 1.7 1.5 1.3 -40°C 1.1 25°C 0.9 85°C 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 37-132. DNL error vs. VREF. T = 25C, VCC = 3.6V. 4.5 4.0 DAC DNL [LSB] 3.5 3.0 2.5 2.0 1.5 1.0 -40°C 25°C 85°C 0.5 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-133. DAC noise vs. temperature. VCC = 3.0V, VREF = 2.0V . 0.2 0.195 Noise[mV RMS] 0.19 0.185 0.18 0.175 0.17 0.165 0.
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37.2.5 Analog Comparator Characteristics Figure 37-134. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 13 12 85°C VHYST [mV] 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-135. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 27 85°C 26 25 VHYST [mV] 24 25°C 23 22 21 -40°C 20 19 18 17 16 15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-136. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 45 85°C 43 25°C 41 VHYST [mV] 39 -40°C 37 35 33 31 29 27 1.6 2.1 2.6 3.1 3.6 VCC [V] Figure 37-137. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 73 85°C 70 67 VHYST [mV] 64 25°C 61 58 -40°C 55 52 49 46 1.6 2.1 2.6 3.1 3.
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Figure 37-138. Analog comparator current source vs. calibration value. Temperature = 25°C. 8.2 ICURRENTSOURCE [µA] 7.4 6.6 5.8 5 3.6 V 4.2 3.0 V 2.7 V 3.4 2.2 V 1.8 V 1.6 V 2.6 1.8 0 2 4 6 8 10 12 14 16 CURRCALIBA[3..0] Figure 37-139. Analog comparator current source vs. calibration value. VCC = 3.0V. 6.5 6.2 ICURRENTSOURCE [µA] 5.9 5.6 5.3 5 4.7 4.4 4.1 -40°C 25°C 85°C 3.8 3.5 0 2 4 6 8 10 12 14 16 CURRCALIBA[3..
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Figure 37-140. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.15 0.12 INL [LSB] 0.09 0.06 0.03 0 -0.03 -0.06 -0.09 0 8 16 24 32 40 48 56 64 SCALEFAC 37.2.6 Internal 1.0V reference Characteristics Figure 37-141. ADC/DAC Internal 1.0V reference vs. temperature. 1.005 1.004 Bandgap Voltage [V] 1.003 1.003 1.002 1.002 1.001 1.6 V 1.000 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 1.000 0.999 0.
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37.2.7 BOD Characteristics Figure 37-142. BOD thresholds vs. temperature. BOD level = 1.6V. 1.64 Rising Vcc 1.64 1.64 VBOT [V] 1.64 1.64 1.64 1.64 1.63 Falling Vcc 1.63 1.63 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-143. BOD thresholds vs. temperature. BOD level = 3.0V. 3.09 3.08 Rising Vcc 3.07 VBOT [V] 3.06 3.05 3.04 Falling Vcc 3.03 3.02 3.
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37.2.8 External Reset Characteristics Figure 37-144. Minimum Reset pin pulse width vs. VCC. 136 129 122 tRST [ns] 115 108 101 85°C 94 25°C -40°C 87 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-145. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 37-146. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 105 IRESET [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 37-147. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 144 126 IRESET [µA] 108 90 72 54 36 -40°C 25°C 85°C 18 0 0.0 0.4 0.7 1.1 1.4 1.8 2.1 2.5 2.8 3.2 3.
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Figure 37-148. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.20 -40°C 25°C 85°C 2.05 VTHRESHOLD [V] 1.90 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-149. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.5 1.3 1.2 1.0 0.9 0.7 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.2.9 Power-on Reset Characteristics Figure 37-150. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 3.09 3.08 Rising Vcc 3.07 VBOT [V] 3.06 3.05 3.04 Falling Vcc 3.03 3.02 3.
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37.2.10 Oscillator Characteristics 37.2.10.1 Ultra Low-Power internal oscillator Figure 37-151. Ultra Low-Power internal oscillator frequency vs. temperature. 35.3 35.0 Frequency [kHz] 34.7 34.4 34.1 33.8 33.5 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 33.2 32.9 32.6 32.3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 37.2.10.2 32.768kHz Internal Oscillator Figure 37-152. 32.768kHz internal oscillator frequency vs. temperature. 32.85 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 32.
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Figure 37-153. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 49 46 Frequency [kHz] 43 40 37 34 31 28 25 22 0 30 60 90 120 150 180 210 240 270 RC32KCAL[7..0] 37.2.10.3 2MHz Internal Oscillator Figure 37-154. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.13 2.11 Frequency [MHz] 2.10 2.08 2.07 2.05 2.04 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.02 2.01 1.
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Figure 37-155. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.01 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 2.01 Frequency [MHz] 2.01 2.00 2.00 1.99 1.99 1.99 1.98 1.98 -45 -30 -15 0 15 30 45 60 75 90 Temperature [°C] Figure 37-156. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.29 % Frequency Step Size [%] 0.27 % 0.25 % 0.23 % 0.21 % 0.19 % -40°C 0.17 % 85°C 25°C 0.15 % 0.
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37.2.10.4 32MHz Internal Oscillator Figure 37-157. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.2 34.8 Frequency [MHz] 34.4 34.0 33.6 33.2 32.8 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.4 32.0 31.6 -45 -30 -15 0 15 30 45 60 75 90 Temperature [°C] Figure 37-158. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 1.6 V 1.8 V 2.2 V 2.7 V 3.6 V 3.0 V 32.05 Frequency [MHz] 32.00 31.95 31.90 31.85 31.80 31.75 31.
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Figure 37-159. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 % Frequency Step Size [%] 0.31 % 0.28 % 0.25 % 0.22 % 25°C 0.19 % 0.16 % 85°C 0.13 % -40°C 0.10 % 0.07 % 0 16 32 48 64 80 96 112 128 CALA Figure 37-160. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V. Frequency Step Size [%] 3.30 % 2.80 % 2.30 % 1.80 % 1.30 % -40°C 25°C 85°C 0.
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37.2.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-161. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 52.5 52.0 Frequency [MHz] 51.5 51.0 50.5 50.0 49.5 49.0 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 48.5 48.0 47.5 -45 -30 -15 0 15 30 45 60 75 90 Temperature [°C] Figure 37-162. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.2 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V Frequency [MHz] 48.1 48 47.9 47.8 1.
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Figure 37-163. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 % Frequency Step Size [%] 0.31 % 0.28 % 0.25 % 0.22 % -40°C 25°C 0.19 % 0.16 % 85°C 0.13 % 0.10 % 0.07 % 0 16 32 48 64 80 96 112 128 CALA 37.2.11 Two-Wire Interface characteristics Figure 37-164. SDA hold time vs. temperature.
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Figure 37-165. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.2.12 PDI characteristics Figure 37-166. Maximum PDI frequency vs. VCC. 34.5 -40°C 25°C 85°C Maximum Frequency [MHz] 32.0 29.5 27.0 24.5 22.0 19.5 17.0 14.5 12.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.3 ATxmega192A3U 37.3.1 Current consumption 37.3.1.1 Active mode supply current ICC [µA] Figure 37-167. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [MHz] 0.7 0.8 0.9 1.0 Figure 37-168. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.3V 12 3.0V 10 ICC [mA] 2.7V 8 6 2.2V 4 1.
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Figure 37-169. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 450 -40°C 400 25°C ICC [µA] 350 85°C 300 250 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-170. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 1000 -40°C 25°C 85°C 900 ICC [µA] 800 700 600 500 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-171. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1800 -40°C 1600 25°C 85°C ICC [µA] 1400 1200 1000 800 600 400 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-172. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 -40°C 25°C 85°C 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-173. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 16 -40°C 15 25°C ICC [mA] 14 85°C 13 12 11 10 9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.3.1.2 Idle mode supply current Figure 37-174. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.3V 160 3.0V 140 2.7V ICC [µA] 120 100 2.2V 80 1.8V 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 37-175. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.3V 5 3.0V 2.7V ICC [mA] 4 3 2.2V 2 1 1.8V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-176. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35 85°C -40°C 34 25°C ICC [µA] 33 32 31 30 29 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-177. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-178. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 500 -40°C 25°C 85°C 450 ICC [µA] 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-179. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.3 -40°C 25°C 85°C 2.1 I CC [mA] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-180. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 6.7 -40°C 6.4 25°C 6.1 85°C ICC [mA] 5.8 5.5 5.2 4.9 4.6 4.3 4.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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37.3.1.3 Power-down mode supply current Figure 37-181. Power-down mode supply current vs. VCC. All functions disabled. 2.4 85°C 2.1 ICC [µA] 1.8 1.5 1.2 0.9 0.6 0.3 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-182. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 3.5 85°C 3.2 ICC [µA] 2.9 2.6 2.3 2.0 1.7 25°C -40°C 1.4 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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37.3.1.4 Power-save mode supply current Figure 37-183. Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.1.5 Standby mode supply current Figure 37-184. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 7.5 ICC [µA] 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.
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Figure 37-185. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.2 I/O Pin Characteristics 37.3.2.1 Pull-up Figure 37-186. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 80 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 37-187. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 37-188. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
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37.3.2.2 Output Voltage vs. Sink/Source Current Figure 37-189. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 0.9 -40°C 0.7 25°C 85°C 0.5 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 37-190. I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 VPIN [V] 2.5 2.0 1.5 1.0 -40°C 0.
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Figure 37-191. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 -30 -25 -20 -15 -10 -5 0 I PIN [mA] Figure 37-192. I/O pin output voltage vs. source current. 4.0 3.6V 3.5 3.3V VPIN [V] 3.0 2.7V 2.5 2.2V 2.0 1.8V 1.5 1.
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Figure 37-193. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-194. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 0.9 25°C 85°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Figure 37-195. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 25°C -40°C VPIN [V] 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 35 IPIN [mA] Figure 37-196. I/O pin output voltage vs. sink current. 1.5 1.8V VPIN [V] 1.2 2.2V 0.9 2.7V 3.3V 3.6V 0.6 0.
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37.3.2.3 Thresholds and Hysteresis Figure 37-197. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.85 1.70 VIH 1.55 VIL VThreshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-198. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 25°C 85°C VTHRESHOLD [V] 1.6 1.4 1.2 1.0 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-199. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.7 -40°C 25°C 85°C VTRESHOLD [V] 1.5 1.3 1.1 0.9 0.7 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-200. I/O pin input hysteresis vs. VCC. 350 VHYSTERESIS [mV] 300 250 200 150 -40°C 25°C 85°C 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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37.3.3 ADC Characteristics Figure 37-201. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.7 1.6 1.5 INL [LSB] 1.4 Differential mode 1.3 1.2 Single-ended unsigned mode 1.1 1.0 0.9 Single-ended signed mode 0.8 0.7 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1550 1700 1850 2000 VREF [V] Figure 37-202. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 1.4 Differential mode 1.3 Single-ended unsigned mode INL [LSB] 1.2 1.1 1.0 0.
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Figure 37-203. INL error vs. input code. 2.0 1.5 1.0 INL [LSB] 0.5 0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 ADC input code 2560 3072 3584 4096 Figure 37-204. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.80 0.75 DNL [LSB] 0.70 Differential mode 0.65 Single-endedsigned mode 0.60 0.55 Single-ended unsigned mode 0.50 0.45 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-205. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. DNL [LSB] 0.70 0.65 Differential mode 0.60 Single-ended signed mode 0.55 0.50 Single-ended unsigned mode 0.45 0.40 0.35 0.50 0.65 0.80 0.95 1.10 1.25 1.40 1.55 1.70 1.85 2.00 Sampling speed [MS/s] Figure 37-206. DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.
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Figure 37-207. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 4 Gain error [mV] 2 Single-ended signed mode 0 -2 Single-ended unsigned mode -4 Differential mode -6 -8 -10 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Figure 37-208. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 3.0 2.5 Gain Error [mV] 2.0 1.5 Single-ended signed mode 1.0 0.5 0 Single-ended unsigned mode -0.5 -1.0 -1.5 -2.0 1.
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Figure 37-209. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.1 Offset [mV] -1.2 -1.3 Differential mode -1.4 -1.5 -1.6 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 Figure 37-210. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 1 0 1V mode -1 Gain error [mV] -2 1.5V mode -3 -4 2V mode -5 -6 2.
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Figure 37-211. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.5 Offset error [mV] -0.6 -0.7 -0.8 Differential mode -0.9 -1.0 -1.1 -1.2 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 37-212. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.30 Single-ended signed mode Noise [mV RMS] 1.15 Single-ended unsigned mode 1.00 0.85 0.70 0.55 Differential mode 0.40 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-213. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended signed mode Noise [mV RMS] 1.1 1.0 0.9 Single-ended unsigned mode 0.8 0.7 0.6 0.5 Differential mode 0.4 0.3 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.4 DAC Characteristics Figure 37-214. DAC INL error vs. VREF. VCC = 3.6V. 3.1 2.9 2.7 INL [LSB] 2.5 2.3 2.1 1.9 1.7 -40°C 1.5 1.3 25°C 1.1 85°C 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-215. DNL error vs. VREF. T = 25C, VCC = 3.6V. 1.4 1.3 DNL [LSB] 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -40°C 0.5 0.4 0.3 25°C 85°C 0.2 0.1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 37-216. DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . 0.183 0.181 Noise [mV RMS] 0.179 0.177 0.175 0.173 0.171 0.169 0.167 0.
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37.3.5 Analog Comparator Characteristics Figure 37-217. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 17 85°C -40°C 25°C 16 15 VHYST [mV] 14 13 12 11 10 9 8 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-218. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 35 85°C 34 33 VHYST [mV] 32 31 25°C 30 29 28 -40°C 27 26 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-219. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 40 85°C 38 25°C -40°C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-220. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 75 85°C VHYST [mV] 70 65 25°C 60 -40°C 55 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-221. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 7 I [µA] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 37-222. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.5 I [µA] 6.0 5.5 5.0 4.5 -40°C 25°C 85°C 4.0 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..
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Figure 37-223. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.100 0.075 INL [LSB] 0.050 0.025 25°C 0 -0.025 -0.050 -0.075 -0.100 0 10 20 30 40 50 60 70 SCALEFAC 37.3.6 Internal 1.0V reference Characteristics Figure 37-224. ADC/DAC Internal 1.0V reference vs. temperature. 1.002 3.3V 3.0V 2.7V 1.8V Bandgap voltage [V] 1.000 0.998 0.996 0.994 0.992 0.
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37.3.7 BOD Characteristics Figure 37-225. BOD thresholds vs. temperature. BOD level = 1.6V. 1.632 Rising VCC 1.630 VBOT [V] 1.628 1.626 1.624 1.622 Falling VCC 1.620 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 55 65 75 85 Temperature [°C] Figure 37-226. BOD thresholds vs. temperature. BOD level = 3.0V. 3.08 3.07 Rising VCC VBOT [V] 3.06 3.05 3.04 3.03 Falling VCC 3.02 3.
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37.3.8 External Reset Characteristics Figure 37-227. Minimum Reset pin pulse width vs. VCC. 147 142 137 tRST [ns] 132 127 122 117 112 107 102 85°C 97 -40°C 25°C 92 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-228. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 37-229. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 37-230. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
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Figure 37-231. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.1 2.0 1.9 1.8 VThreshold [V] 1.7 1.6 1.5 1.4 1.3 1.2 -40°C 25°C 1.1 85°C 1.0 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 37-232. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.65 -40°C 25°C 85°C 1.50 1.35 VThreshold [V] 1.20 1.05 0.90 0.75 0.60 0.45 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.
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37.3.9 Power-on Reset Characteristics Figure 37-233. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 85°C ICC [µA] 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.
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37.3.10 Oscillator Characteristics 37.3.10.1 Ultra Low-Power internal oscillator Figure 37-234. Ultra Low-Power internal oscillator frequency vs. temperature. 32.9 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.8 32.7 32.6 32.5 32.4 32.3 32.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 37.3.10.2 32.768kHz Internal Oscillator Figure 37-235. 32.768kHz internal oscillator frequency vs. temperature. 32.85 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.80 32.75 32.70 32.65 32.
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Figure 37-236. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 Frequency [kHz] 45 40 35 30 25 20 0 50 100 150 200 250 300 RC32KCAL[7..0] 37.3.10.3 2MHz Internal Oscillator Figure 37-237. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.18 2.16 Frequency [MHz] 2.14 2.12 2.10 2.08 2.06 2.04 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.
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Figure 37-238. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.008 3.0V 3.3V 2.7V 2.2V 1.8V 2.005 2.002 Frequency [MHz] 1.999 1.996 1.993 1.990 1.987 1.984 1.981 1.978 1.975 -45 -35 -25 -15 -5 5 15 25 35 Temperature [°C] 45 55 65 75 85 Figure 37-239. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.37 0.35 Step size [%] 0.32 0.30 0.27 0.25 0.22 0.20 25°C -40°C 0.
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37.3.10.4 32MHz Internal Oscillator Figure 37-240. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.5 36.0 Frequency [MHz] 35.5 35.0 34.5 34.0 33.5 33.0 3.3V 32.5 3.0V 2.7V 1.8V 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-241. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.0V 3.3V 2.7V 2.2V 1.8V 32.05 32.00 Frequency [MHz] 31.95 31.90 31.85 31.80 31.75 31.
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Figure 37-242. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.39 Step size 0.34 0.29 0.24 25°C 0.19 85°C -40°C 0.14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA Figure 37-243. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
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37.3.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-244. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55 54 Frequency [MHz] 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-245. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.15 3.3V 3.0V 2.7V 2.2V 1.8V 48.05 Frequency [MHz] 47.95 47.85 47.75 47.65 47.55 47.
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Figure 37-246. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.40% Step size 0.35% 0.30% 0.25% 25°C 0.20% 85°C -40°C 0.15% 0 16 32 48 64 80 96 112 128 CALA 37.3.11 Two-Wire Interface characteristics Figure 37-247. SDA hold time vs. temperature.
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Figure 37-248. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.3.12 PDI characteristics fMAX [MHz] Figure 37-249. Maximum PDI frequency vs. VCC. 36 -40°C 31 25°C 85°C 26 21 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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37.4 ATxmega256A3U 37.4.1 Current consumption 37.4.1.1 Active mode supply current ICC [µA] Figure 37-250. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [MHz] 0.7 0.8 0.9 1.0 Figure 37-251. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.3V 12 3.0V 10 ICC [mA] 2.7V 8 6 2.2V 4 1.
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Figure 37-252. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 450 -40°C 400 25°C ICC [µA] 350 85°C 300 250 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-253. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 1000 -40°C 25°C 85°C 900 ICC [µA] 800 700 600 500 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-254. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1800 -40°C 1600 25°C 85°C ICC [µA] 1400 1200 1000 800 600 400 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-255. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 -40°C 25°C 85°C 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-256. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 16 -40°C 15 25°C ICC [mA] 14 85°C 13 12 11 10 9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.4.1.2 Idle mode supply current Figure 37-257. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.3V 160 3.0V 140 2.7V ICC [µA] 120 100 2.2V 80 1.8V 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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Figure 37-258. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.3V 5 3.0V 2.7V ICC [mA] 4 3 2.2V 2 1 1.8V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-259. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35 85°C -40°C 34 25°C ICC [µA] 33 32 31 30 29 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-260. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-261. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 500 -40°C 25°C 85°C 450 ICC [µA] 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-262. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.3 -40°C 25°C 85°C 2.1 I CC [mA] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-263. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 6.7 -40°C 6.4 25°C 6.1 85°C ICC [mA] 5.8 5.5 5.2 4.9 4.6 4.3 4.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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37.4.1.3 Power-down mode supply current Figure 37-264. Power-down mode supply current vs. VCC. All functions disabled. 2.4 85°C 2.1 ICC [µA] 1.8 1.5 1.2 0.9 0.6 0.3 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-265. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 3.5 85°C 3.2 ICC [µA] 2.9 2.6 2.3 2.0 1.7 25°C -40°C 1.4 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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37.4.1.4 Power-save mode supply current Figure 37-266. Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.4.1.5 Standby mode supply current Figure 37-267. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 7.5 ICC [µA] 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.
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Figure 37-268. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.4.2 I/O Pin Characteristics 37.4.2.1 Pull-up Figure 37-269. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 80 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 37-270. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 37-271. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
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37.4.2.2 Output Voltage vs. Sink/Source Current Figure 37-272. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 0.9 -40°C 0.7 25°C 85°C 0.5 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 37-273. I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 VPIN [V] 2.5 2.0 1.5 1.0 -40°C 0.
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Figure 37-274. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 -30 -25 -20 -15 -10 -5 0 I PIN [mA] Figure 37-275. I/O pin output voltage vs. source current. 4.0 3.6V 3.5 3.3V VPIN [V] 3.0 2.7V 2.5 2.2V 2.0 1.8V 1.5 1.
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Figure 37-276. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-277. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 0.9 25°C 85°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Figure 37-278. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 25°C -40°C VPIN [V] 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 35 IPIN [mA] Figure 37-279. I/O pin output voltage vs. sink current. 1.5 1.8V VPIN [V] 1.2 2.2V 0.9 2.7V 3.3V 3.6V 0.6 0.
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37.4.2.3 Thresholds and Hysteresis Figure 37-280. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.85 1.70 VIH 1.55 VIL VThreshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-281. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 25°C 85°C VTHRESHOLD [V] 1.6 1.4 1.2 1.0 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-282. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.7 -40°C 25°C 85°C VTRESHOLD [V] 1.5 1.3 1.1 0.9 0.7 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-283. I/O pin input hysteresis vs. VCC. 350 VHYSTERESIS [mV] 300 250 200 150 -40°C 25°C 85°C 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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37.4.3 ADC Characteristics Figure 37-284. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.7 1.6 1.5 INL [LSB] 1.4 Differential mode 1.3 1.2 Single-ended unsigned mode 1.1 1.0 0.9 Single-ended signed mode 0.8 0.7 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1550 1700 1850 2000 VREF [V] Figure 37-285. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 1.4 Differential mode 1.3 Single-ended unsigned mode INL [LSB] 1.2 1.1 1.0 0.
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Figure 37-286. INL error vs. input code. 2.0 1.5 1.0 INL [LSB] 0.5 0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 ADC input code 2560 3072 3584 4096 Figure 37-287. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.80 0.75 DNL [LSB] 0.70 Differential mode 0.65 Single-endedsigned mode 0.60 0.55 Single-ended unsigned mode 0.50 0.45 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-288. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. DNL [LSB] 0.70 0.65 Differential mode 0.60 Single-ended signed mode 0.55 0.50 Single-ended unsigned mode 0.45 0.40 0.35 0.50 0.65 0.80 0.95 1.10 1.25 1.40 1.55 1.70 1.85 2.00 Sampling speed [MS/s] Figure 37-289. DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.
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Figure 37-290. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 4 Gain error [mV] 2 Single-ended signed mode 0 -2 Single-ended unsigned mode -4 Differential mode -6 -8 -10 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Figure 37-291. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 3.0 2.5 Gain Error [mV] 2.0 1.5 Single-ended signed mode 1.0 0.5 0 Single-ended unsigned mode -0.5 -1.0 -1.5 -2.0 1.
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Figure 37-292. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.1 Offset [mV] -1.2 -1.3 Differential mode -1.4 -1.5 -1.6 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 Figure 37-293. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 1 0 1V mode -1 Gain error [mV] -2 1.5V mode -3 -4 2V mode -5 -6 2.
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Figure 37-294. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.5 Offset error [mV] -0.6 -0.7 -0.8 Differential mode -0.9 -1.0 -1.1 -1.2 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 37-295. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.30 Single-ended signed mode Noise [mV RMS] 1.15 Single-ended unsigned mode 1.00 0.85 0.70 0.55 Differential mode 0.40 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-296. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended signed mode Noise [mV RMS] 1.1 1.0 0.9 Single-ended unsigned mode 0.8 0.7 0.6 0.5 Differential mode 0.4 0.3 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.4.4 DAC Characteristics Figure 37-297. DAC INL error vs. VREF. VCC = 3.6V. 3.1 2.9 2.7 INL [LSB] 2.5 2.3 2.1 1.9 1.7 -40°C 1.5 1.3 25°C 1.1 85°C 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 37-298. DNL error vs. VREF. T = 25C, VCC = 3.6V. 1.4 1.3 DNL [LSB] 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -40°C 0.5 0.4 0.3 25°C 85°C 0.2 0.1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 37-299. DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . 0.183 0.181 Noise [mV RMS] 0.179 0.177 0.175 0.173 0.171 0.169 0.167 0.
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37.4.5 Analog Comparator Characteristics Figure 37-300. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 17 85°C -40°C 25°C 16 15 VHYST [mV] 14 13 12 11 10 9 8 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-301. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 35 85°C 34 33 VHYST [mV] 32 31 25°C 30 29 28 -40°C 27 26 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-302. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 40 85°C 38 25°C -40°C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-303. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 75 85°C VHYST [mV] 70 65 25°C 60 -40°C 55 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 37-304. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 7 I [µA] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 37-305. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.5 I [µA] 6.0 5.5 5.0 4.5 -40°C 25°C 85°C 4.0 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..
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Figure 37-306. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.100 0.075 INL [LSB] 0.050 0.025 25°C 0 -0.025 -0.050 -0.075 -0.100 0 10 20 30 40 50 60 70 SCALEFAC 37.4.6 Internal 1.0V reference Characteristics Figure 37-307. ADC/DAC Internal 1.0V reference vs. temperature. 1.002 3.3V 3.0V 2.7V 1.8V Bandgap voltage [V] 1.000 0.998 0.996 0.994 0.992 0.
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37.4.7 BOD Characteristics Figure 37-308. BOD thresholds vs. temperature. BOD level = 1.6V. 1.632 Rising VCC 1.630 VBOT [V] 1.628 1.626 1.624 1.622 Falling VCC 1.620 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 55 65 75 85 Temperature [°C] Figure 37-309. BOD thresholds vs. temperature. BOD level = 3.0V. 3.08 3.07 Rising VCC VBOT [V] 3.06 3.05 3.04 3.03 Falling VCC 3.02 3.
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37.4.8 External Reset Characteristics Figure 37-310. Minimum Reset pin pulse width vs. VCC. 147 142 137 tRST [ns] 132 127 122 117 112 107 102 85°C 97 -40°C 25°C 92 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 37-311. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
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Figure 37-312. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 37-313. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
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Figure 37-314. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.1 2.0 1.9 1.8 VThreshold [V] 1.7 1.6 1.5 1.4 1.3 1.2 -40°C 25°C 1.1 85°C 1.0 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 37-315. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.65 -40°C 25°C 85°C 1.50 1.35 VThreshold [V] 1.20 1.05 0.90 0.75 0.60 0.45 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.
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37.4.9 Power-on Reset Characteristics Figure 37-316. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 85°C ICC [µA] 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.
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37.4.10 Oscillator Characteristics 37.4.10.1 Ultra Low-Power internal oscillator Figure 37-317. Ultra Low-Power internal oscillator frequency vs. temperature. 32.9 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.8 32.7 32.6 32.5 32.4 32.3 32.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 37.4.10.2 32.768kHz Internal Oscillator Figure 37-318. 32.768kHz internal oscillator frequency vs. temperature. 32.85 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.80 32.75 32.70 32.65 32.
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Figure 37-319. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 Frequency [kHz] 45 40 35 30 25 20 0 50 100 150 200 250 300 RC32KCAL[7..0] 37.4.10.3 2MHz Internal Oscillator Figure 37-320. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.18 2.16 Frequency [MHz] 2.14 2.12 2.10 2.08 2.06 2.04 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.
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Figure 37-321. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.008 3.0V 3.3V 2.7V 2.2V 1.8V 2.005 2.002 Frequency [MHz] 1.999 1.996 1.993 1.990 1.987 1.984 1.981 1.978 1.975 -45 -35 -25 -15 -5 5 15 25 35 Temperature [°C] 45 55 65 75 85 Figure 37-322. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.37 0.35 Step size [%] 0.32 0.30 0.27 0.25 0.22 0.20 25°C -40°C 0.
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37.4.10.4 32MHz Internal Oscillator Figure 37-323. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.5 36.0 Frequency [MHz] 35.5 35.0 34.5 34.0 33.5 33.0 3.3V 32.5 3.0V 2.7V 1.8V 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-324. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.0V 3.3V 2.7V 2.2V 1.8V 32.05 32.00 Frequency [MHz] 31.95 31.90 31.85 31.80 31.75 31.
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Figure 37-325. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.39 Step size 0.34 0.29 0.24 25°C 0.19 85°C -40°C 0.14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA Figure 37-326. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
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37.4.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-327. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55 54 Frequency [MHz] 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-328. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.15 3.3V 3.0V 2.7V 2.2V 1.8V 48.05 Frequency [MHz] 47.95 47.85 47.75 47.65 47.55 47.
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Figure 37-329. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.40% Step size 0.35% 0.30% 0.25% 25°C 0.20% 85°C -40°C 0.15% 0 16 32 48 64 80 96 112 128 CALA 37.4.11 Two-Wire Interface characteristics Figure 37-330. SDA hold time vs. temperature.
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Figure 37-331. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.4.12 PDI characteristics fMAX [MHz] Figure 37-332. Maximum PDI frequency vs. VCC. 36 -40°C 31 25°C 85°C 26 21 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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38. Errata 38.1 ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U 38.1.1 Rev. G  AWeX fault protection restore is not done correct in Pattern Generation Mode 1. AWeX fault protection restore is not done correct in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels.
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39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8386D – 03/2014 1. 2. 39.2 Updated “Port A - alternate functions.” on page 55:  Removed ACDP POS from the Table 32-1 on page 55 Updated “Port B - alternate functions.” on page 55:  ACDB POS changed to ADCB POS/GAINPOS in the Table 32-2 on page 55 8386C – 02/2013 1.
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39.4 4. Updated “Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.” on page 64. 5. Updated “Electrical Characteristics” on page 67. 6. Updated “Typical Characteristics” on page 155. 7. Several changes in “Typical Characteristics” 8386A – 07/2011 1. Initial revision.
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 22 11.1 11.2 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12. System Control and Reset . . . . . . . . . . . . . . . .
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22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24. USART . . . . . . . . . . . . . . . . .
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36.4 ATxmega256A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 37.1 37.2 37.3 37.4 ATxmega64A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATxmega128A3U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATxmega192A3U . . . . . . . . . . . . . . . . . . . . . . . . . . .
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