Datasheet

5
8116J–AVR–06/2013
XMEGA A3B
Not recommended for new designs -
Use ATxmega256A3BU
The XMEGA A3B devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
3.1 Block Diagram
Figure 3-1. XMEGA A3B Block Diagram
PE[0..5]
PORT E (6)
TCE0:1
USARTE0
TWIE
TCF0
USARTF0
PORT F (7)
Power
Supervision
POR/BOD &
RESET
DMA
Controller
BUS
Controller
SRAM
OCD
PDI
CPU
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Control
Event System
Controller
JTAG
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
Flash EEPROM
NVM Controller
DES
AES
IRCOM
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PORT D (8)
TCD0:1
USARTD0:1
SPID
EVENT ROUTING NETWORK
PF[0..4,6..7]
V
BAT
Power
Supervision
Battery
Backup
Controller
Real Time
Counter
32.768 kHz
XOSC
VBAT
TOSC1
TOSC2
Oscillator
Circuits/
Clock
Generation
PORT R (2)
XTAL1
XTAL2
PR[0..1]
PORT A (8)
PORT B (8)
ADCA
ACA
DACB
ADCB
ACB
PA[0..7]
PB[0..7]/
JTAG
Int. Ref.
AREFA
AREFB
Tempref
VCC/10