Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 (9x9) 8/16-Bit 32 MHz I/O number 49

Features

• High-performance, Low-power 8/16-bit Atmel

AVR

XMEGA

Microcontroller

• Non-volatile Program and Data Memories

– 256 KB of In-System Self-Programmable Flash

– 8 KB Boot Code Section with Independent Lock Bits

– 4 KB EEPROM

– 16 KB Internal SRAM

• Peripheral Features

– Four-channel DMA Controller with support for external requests

– Eight-channel Event System

– Seven 16-bit Timer/Counters

Four Timer/Counters with 4 Output Compare or Input Capture channels

Three Timer/Counters with 2 Output Compare or Input Capture channels

High-Resolution Extension on all Timer/Counters

Advanced Waveform Extension on one Timer/Counter

– Six USARTs

IrDA modulation/demodulation for one USART

– Two Two-Wire Interfaces with dual address match (I

C and SMBus compatible)

– Two SPI (Serial Peripheral Interface) peripherals

– AES and DES Crypto Engine

– 32-bit Real Time Counter with separate Oscillator and Battery Backup System

– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters

– One Two-channel, 12-bit, 1 Msps Digital to Analog Converters

– Four Analog Comparators with Window compare function

– External Interrupts on all General Purpose I/O pins

– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal and External Clock Options with PLL

– Programmable Multi-level Interrupt Controller

– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby

– Advanced Programming, Test and Debugging Interfaces

JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming

PDI (Program and Debug Interface) for programming and debugging

• I/O and Packages

– 49 Programmable I/O Lines

– 64-lead TQFP

– 64-pad QFN/MLF

• Operating Voltage

– 1.6 – 3.6V

• Speed performance

– 0 – 12 MHz @ 1.6 – 3.6V

– 0 – 32 MHz @ 2.7 – 3.6V

Typical Applications

• Industrial control • Climate control • Hand-held battery applications

• Factory automation • ZigBee • Power tools

• Building control • Motor control • HVAC

• Board control • Networking • Metering

• White Goods • Optical • Medical Applications

8/16-bit

XMEGA A3B

Microcontroller

ATxmega256A3B

Preliminary

Not recommended for

new designs - Use

ATxmega256A3BU

8116J–AVR–06/2013

Not recommended for new designs -

Use ATxmega256A3BU

Summary of content (109 pages)

PAGE 1
Features • High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller • Non-volatile Program and Data Memories • • • • • – 256 KB of In-System Self-Programmable Flash – 8 KB Boot Code Section with Independent Lock Bits – 4 KB EEPROM – 16 KB Internal SRAM Peripheral Features – Four-channel DMA Controller with support for external requests – Eight-channel Event System – Seven 16-bit Timer/Counters Four Timer/Counters with 4 Output Compare or Input Capture channels Three Timer/Counters with
PAGE 2
XMEGA A3B 1. Ordering Information Flash E2 SRAM Speed (MHz) Power Supply Package(1)(2)(3) ATxmega256A3B-AU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V 64A ATxmega256A3B-MH 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V 64M2 Ordering Code Notes: Temp -40C - 85C 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2.
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XMEGA A3B 2. Pinout/Block Diagram Block diagram and pinout. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 INDEXCORNER PF6 VCC GND VBAT PF4 PF3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI PF7 Figure 2-1.
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XMEGA A3B 3. Overview The XMEGA™A3B is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR ® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A3B achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
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XMEGA A3B The XMEGA A3B devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 Block Diagram Figure 3-1. XMEGA A3B Block Diagram PR[0..1] XTAL1 PORT R (2) XTAL2 Oscillator Circuits/ Clock Generation Watchdog Oscillator Watchdog Timer DATA BUS PA[0..
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XMEGA A3B 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA A Manual • XMEGA Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.
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XMEGA A3B 6. AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture • • • • • • • 6.
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XMEGA A3B concept enables instructions to be executed in every clock cycle. The program memory is InSystem Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU cycle, the operation is performed on two Register File operands, and the result is stored back in the Register File.
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XMEGA A3B 7. Memories 7.
PAGE 10
XMEGA A3B 7.3 In-System Programmable Flash Program Memory The XMEGA A3B devices contain On-chip In-System Programmable Flash memory for program storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations.
PAGE 11
XMEGA A3B Figure 7-2. Data Memory Map (Hexadecimal address) 1000 EEPROM (4 KB) 1FFF 2000 5FFF 7.4.1 Internal SRAM (16 KB) I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory.
PAGE 12
XMEGA A3B 7.5 Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the available XMEGA A3 devices is shown in Table 7-1 on page 12.
PAGE 13
XMEGA A3B 7.7 Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing.
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XMEGA A3B 8. DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer • • • • • 8.
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XMEGA A3B 9. Event System 9.1 Features • • • • • • • • 9.
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XMEGA A3B Figure 9-1. Event system block diagram. PORTx ClkSYS CPU ADCx RTC Event Routing Network DACx IRCOM ACx T/Cxn DMAC The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU). All events from all peripherals are always routed into the Event Routing Network.
PAGE 17
XMEGA A3B 10. System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: • • • • • • 10.2 – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator – 32 kHz Ultra Low Power (ULP) oscillator External clock options – 0.4 - 16 MHz Crystal Oscillator – 32.
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XMEGA A3B Figure 10-1. Clock system overview clkULP WDT/BOD 32 kHz ULP Internal Oscillator clkRTC RTC 32.768 kHz Calibrated Internal Oscillator PERIPHERALS ADC 2 MHz Run-Time Calibrated Internal Oscillator 32 MHz Run-time Calibrated Internal Oscillator DAC CLOCK CONTROL clkPER UNIT with PLL and Prescaler PORTS ... DMA INTERRUPT 32.768 KHz Crystal Oscillator EVSYS RAM 0.
PAGE 19
XMEGA A3B 10.3.3 32.768 kHz Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 - 16 MHz Crystal Oscillator The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz. 10.3.
PAGE 20
XMEGA A3B 11. Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A3B provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. The application code decides when and what sleep mode to enter.
PAGE 21
XMEGA A3B 11.3.5 Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.
PAGE 22
XMEGA A3B 12. System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset The Watchdog Timer runs from separate, dedicated oscillator – Brown-Out Reset Accurate, programmable Brown-Out levels – JTAG Reset – PDI reset – Software reset • Asynchronous reset – No running clock in the device is required for reset • Reset status register 12.
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XMEGA A3B 12.3.5 JTAG reset The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details. 12.3.6 PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 12.3.7 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 12.4 12.4.1 WDT - Watchdog Timer Features • 11 selectable timeout periods, from 8 ms to 8s.
PAGE 24
XMEGA A3B 13. Battery Backup System 13.1 Features • Battery Backup voltage supply from dedicated VBAT power pin for: – One Ultra Low-power 32-bit Real Time Counter – One 32.
PAGE 25
XMEGA A3B Figure 13-1.
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XMEGA A3B 14. PMIC - Programmable Multi-level Interrupt Controller 14.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts (round-robin or fixed) – Non-Maskable Interrupts (NMI) • Interrupt vectors can be moved to the start of the Boot Section 14.
PAGE 27
XMEGA A3B Table 14-1.
PAGE 28
XMEGA A3B 15. I/O Ports 15.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events • • • • • • • • • • 15.
PAGE 29
XMEGA A3B 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) DIRn OUTn Pn INn 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
PAGE 30
XMEGA A3B Figure 15-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 15-6.
PAGE 31
XMEGA A3B 15.4 Input sensing • • • • Sense both edges Sense rising edges Sense falling edges Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 31. Figure 15-7.
PAGE 32
XMEGA A3B 16. T/C - 16-bit Timer/Counter with PWM 16.1 Features • Seven 16-bit Timer/Counters • • • • • • • • • • • • 16.
PAGE 33
XMEGA A3B Figure 16-1.
PAGE 34
XMEGA A3B 17. AWEX - Advanced Waveform Extension 17.1 Features • • • • • • • • 17.
PAGE 35
XMEGA A3B 18. Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 18.2 Overview The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4.
PAGE 36
XMEGA A3B 19. RTC32 - 32-bit Real-Time Counter 19.1 Features • • • • • • 32-bit resolution One 32-bit Compare register One 32-bit Period register Clear Timer on overflow Optional Interrupt/ Event on overflow and compare match Selectable clock reference – 1.024 kHz – 1 Hz • Isolated VBAT power domain with dynamic switch over from/to VCC power domain’ 19.1.
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XMEGA A3B 20. TWI - Two Wire Interface 20.1 Features • • • • • • • • • • • • 20.
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XMEGA A3B 21. SPI - Serial Peripheral Interface 21.1 Features • • • • • • • • • 21.
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XMEGA A3B 22. USART 22.1 Features • • • • • • • • • • • • • • • 22.
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XMEGA A3B 23. IRCOM - IR Communication Module 23.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built in filtering • Can be connected to and used by one USART at a time 23.
PAGE 41
XMEGA A3B 24. Crypto Engine 24.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • AES Crypto Module – Encryption and Decryption – Support 128-bit keys – Support XOR data load mode to the State memory for Cipher Block Chaining – Encryption/Decryption in 375 clock cycles per 16-byte block 24.
PAGE 42
XMEGA A3B 25. ADC - 12-bit Analog to Digital Converter 25.1 Features • • • • • • • • • • • • • 25.
PAGE 43
XMEGA A3B Figure 25-1. ADC overview Channel C MUX selection Channel D MUX selection Configuration Reference selection Pin inputs Channel A Register Channel B Register Pin inputs Internal inputs Channel A MUX selection Channel B MUX selection ADC Channel C Register 1-64 X Event Trigger Channel D Register Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.
PAGE 44
XMEGA A3B 26. DAC - 12-bit Digital to Analog Converter 26.1 Features • • • • • • • • 26.2 One DAC with 12-bit resolution Up to 1 Msps conversion rate for each DAC Flexible conversion range Multiple trigger sources 1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC Built-in offset and gain calibration High drive capabilities Low Power Mode Overview The XMEGA A3B devices features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 26-1 on page 44.
PAGE 45
XMEGA A3B 27. AC - Analog Comparator 27.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – 0, 20 mV, 50 mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on the port – Output from the DAC – Bandgap reference voltage. – Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
PAGE 46
XMEGA A3B Figure 27-1.
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XMEGA A3B 27.3 Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page 46.
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XMEGA A3B 28. OCD - On-chip Debug 28.
PAGE 49
XMEGA A3B 29. Program and Debug Interfaces 29.1 Features • • • • • 29.2 PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) JTAG Interface (IEEE std. 1149.1 compliant) Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) Access to the OCD system Programming of Flash, EEPROM, Fuses and Lock Bits Overview The programming and debug facilities are accessed through the JTAG and PDI physical interfaces.
PAGE 50
XMEGA A3B 30. Pinout and Pin Functions The pinout of XMEGA A3B is shown in ”Pinout/Block Diagram” on page 3. In addition to general I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time. 30.1 Alternate Pin Function Description The tables below shows the notation for all pin functions available and describes its function. 30.1.1 30.1.2 30.1.3 30.1.4 30.1.
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XMEGA A3B 30.1.6 30.1.
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XMEGA A3B 30.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. Port A - Alternate functions Table 30-1.
PAGE 53
XMEGA A3B Port C - Alternate functions (Continued) Table 30-3.
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XMEGA A3B Port F - Alternate functions (Continued) Table 30-6. PORT F PIN # INTERRUPT GND 52 SYNC VCC 53 SYNC PF6 54 PF7 55 Table 30-7. PORT R TCF0 USARTF0 Port R- Alternate functions PIN # INTERRUPT PDI XTAL PDI 56 PDI_DATA RESET 57 PRO 58 SYNC XTAL2 PR1 59 SYNC XTAL1 PDI_CLK Table 30-8. Bit Number 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 8116J–AVR–06/2013 ATxmega256A3B Boundary Scan Order Signal Name PQ3.
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XMEGA A3B Bit Number 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 8116J–AVR–06/2013 Signal Name PJ7.Bidir PJ7.Control PJ6.Bidir PJ6.Control PJ5.Bidir PJ5.Control PJ4.Bidir PJ4.Control PJ3.Bidir PJ3.Control PJ2.Bidir PJ2.Control PJ1.Bidir PJ1.Control PJ0.Bidir PJ0.Control PH7.Bidir PH7.Control PH6.Bidir PH6.Control PH5.Bidir PH5.
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XMEGA A3B Bit Number 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8116J–AVR–06/2013 Signal Name PD7.Bidir PD7.Control PD6.Bidir PD6.Control PD5.Bidir PD5.Control PD4.Bidir PD4.Control PD3.Bidir PD3.Control PD2.Bidir PD2.Control PD1.Bidir PD1.Control PD0.Bidir PD0.Control PC7.Bidir PC7.Control PC6.Bidir PC6.Control PC5.Bidir PC5.Control PC4.Bidir PC4.Control PC3.Bidir PC3.
PAGE 57
XMEGA A3B 31. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A3B. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual.
PAGE 58
XMEGA A3B 32.
PAGE 59
XMEGA A3B Mnemonics Operands Description CALL k call Subroutine PC  RET Subroutine Return PC RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate Operation Flags #Clocks k None 3 / 4(1)  STACK None 4 / 5(1) PC  STACK I 4 / 5(1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register
PAGE 60
XMEGA A3B Mnemonics Operands Description Flags #Clocks LD Rd, -Y Load Indirect and Pre-Decrement Y Rd   Y-1 (Y) None 2(1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd  (Y + q) None 2(1)(2) LD Rd, Z Load Indirect Rd  (Z) None 1(1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z   (Z), Z+1 None 1(1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd   Z - 1, (Z) None 2(1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2(1)(2)
PAGE 61
XMEGA A3B Mnemonics Operands Description Operation ROL Rd Rotate Left Through Carry ROR Rd ASR Flags #Clocks Rd(0) Rd(n+1) C    C, Rd(n), Rd(7) Z,C,N,V,H 1 Rotate Right Through Carry Rd(7) Rd(n) C    C, Rd(n+1), Rd(0) Z,C,N,V 1 Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)  Rd(7..
PAGE 62
XMEGA A3B 33. Packaging information 33.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
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XMEGA A3B 33.2 64M2 D Marked pin# 1 I D E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1.
PAGE 64
XMEGA A3B 34. Electrical Characteristics 34.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ............................................... 20.
PAGE 65
XMEGA A3B Table 34-1. Symbol Current Consumption Parameter Condition Min Typ Max Units (2) Module current consumption RC32M RC32M w/DFLL 460 Internal 32.768 kHz oscillator as DFLL source RC2M RC2M w/DFLL 101 Internal 32.768 kHz oscillator as DFLL source RC32K PLL ICC 594 134 27 Multiplication factor = 10x 202 Watchdog normal mode 1 BOD Continuous mode 128 BOD Sampled mode 1 Internal 1.00 V ref 80 Temperature reference 74 RTC with int.
PAGE 66
XMEGA A3B 34.3 Operating Voltage and Frequency Table 34-2. Symbol ClkCPU Operating voltage and frequency Parameter CPU clock frequency Condition Min Typ Max VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency of the XMEGA A3B devices is depending on VCC. As shown in Figure 34-1 on page 66 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 34-1. Maximum Frequency vs. Vcc MHz 32 Safe Operating Area 12 1.6 1.
PAGE 67
XMEGA A3B 34.4 Flash and EEPROM Memory Characteristics Table 34-3. Symbol Endurance and Data Retention Parameter Condition Min 25°C 10K 85°C 10K 25°C 100 55°C 25 25°C 80K 85°C 30K 25°C 100 55°C 25 Typ Max Write/Erase cycles Units Cycle Flash Data retention Year Write/Erase cycles Cycle EEPROM Data retention Table 34-4.
PAGE 68
XMEGA A3B 34.5 ADC Characteristics Table 34-5.
PAGE 69
XMEGA A3B 34.6 DAC Characteristics Table 34-7. Symbol DAC Characteristics Parameter Condition INL Integral Non-Linearity VCC = 1.6-3.6V DNL Differential Non-Linearity VCC = 1.6-3.6V Fclk Min Typ VREF = Ext. ref 5 VREF = Ext. ref <±1 External reference voltage 1.1 Reference input impedance 34.7 LSB 1000 ksps AVCC-0.6 V >10 Max output voltage Rload=100k AVCC*0.98 Min output voltage Rload=100k 0.015 Offset factory calibration accuracy Continues mode, VCC=3.0V, VREF = Int 1.
PAGE 70
XMEGA A3B 34.9 Brownout Detection Characteristics Table 34-10. Brownout Detection Characteristics(1) Symbol Parameter Condition Min Typ BOD level 0 falling Vcc 1.62 BOD level 1 falling Vcc 1.9 BOD level 2 falling Vcc 2.17 BOD level 3 falling Vcc 2.43 BOD level 4 falling Vcc 2.68 BOD level 5 falling Vcc 2.96 BOD level 6 falling Vcc 3.22 BOD level 7 falling Vcc 3.49 Max Units V Hysteresis Note: BOD level 0-5 1 % 1. BOD is calibrated on BOD level 0 at 85C. 34.
PAGE 71
XMEGA A3B 34.11 POR Characteristics Table 34-12. Power-on Reset Characteristics Symbol Parameter Condition Min Typ VPOT- POR threshold voltage falling Vcc 1 VPOT+ POR threshold voltage rising Vcc 1.45 Max Units V 34.12 Reset Characteristics Table 34-13. Reset Characteristics Symbol Parameter Condition Min Minimum reset pulse width Reset threshold voltage Typ Max 90 VCC = 2.7 - 3.6V 0.45*VCC VCC = 1.6 - 2.7V 0.42*VCC Units ns V 34.13 Oscillator Characteristics Table 34-14.
PAGE 72
XMEGA A3B Table 34-18. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal Crystal CL [pF] Max ESR [k] 6.5 60 9 35 Table 34-19. Device wake-up time from sleep Symbol Parameter Condition (1) Int. 32.768 kHz RC Idle Sleep, Standby and Extended Standby sleep mode Min Typ(2) Max Units 130 Int. 2 MHz RC 2 Ext. 2 MHz Clock 2 Int. 32 MHz RC 0.17 Int. 32.768 kHz RC 320 Int. 2 MHz RC 10.3 Ext. 2 MHz Clock 4.5 Int. 32 MHz RC 5.
PAGE 73
XMEGA A3B 34.14 VBAT and Battery Backup Characteristics Table 34-20. VBAT and Battery Backup Characteristics Symbol Parameter Condition Min Vbat supply voltage range Typ Vbbbod Vbat power-on slope rate Monotonic rising Vcc Power-loss slope range Monotonic falling Max 3.6 0.2 V V/ms 0.1 main BOD threshold voltage Units 1.8 V/ms V BBBOD required voltage change 1.2 BBBOD threshold voltage 1.7 2.
PAGE 74
XMEGA A3B 35. Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency fSYS = 0 - 1.0 MHz External clock, T = 25°C ICC [uA] 900 800 3.3 V 700 3.0 V 600 2.7 V 500 2.2 V 400 1.8 V 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 35-2. Active Supply Current vs. Frequency fSYS = 1 - 32 MHz External clock, T = 25°C ICC [mA] 20 18 3.3 V 16 3.0 V 14 2.7 V 12 10 8 2.2 V 6 4 1.
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XMEGA A3B Figure 35-3. Active Supply Current vs. Vcc fSYS = 1.0 MHz External Clock 85 °C 25 °C -40 °C 1000 900 800 ICC [uA] 700 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-4. Active Supply Current vs. VCC fSYS = 32.768 kHz internal RC 140 -40 °C 25 °C 85 °C 120 ICC [uA] 100 80 60 40 20 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-5. Active Supply Current vs. Vcc fSYS = 2.0 MHz internal RC 2000 -40 °C 25 °C 85 °C 1800 1600 ICC [uA] 1400 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-6. Active Supply Current vs. Vcc fSYS = 32 MHz internal RC prescaled to 8 MHz 8 -40 °C 25 °C 85 °C 7 6 ICC [mA] 5 4 3 2 1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-7. Active Supply Current vs. Vcc fSYS = 32 MHz internal RC 25 -40 °C 25 °C 85 °C ICC [mA] 20 15 10 5 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 35.2 Idle Supply Current Figure 35-8. Idle Supply Current vs. Frequency fSYS = 0 - 1.0 MHz, T = 25°C 250 3.3 V 3.0 V 200 ICC [uA] 2.7 V 150 2.2 V 1.8 V 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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XMEGA A3B Figure 35-9. Idle Supply Current vs. Frequency fSYS = 1 - 32 MHz, T = 25°C 8 3.3 V 7 3.0 V 6 2.7 V ICC [mA] 5 4 3 2.2 V 2 1.8 V 1 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 35-10. Idle Supply Current vs. Vcc fSYS = 1.0 MHz External Clock 300 85 °C 25 °C -40 °C 250 ICC [uA] 200 150 100 50 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-11. Idle Supply Current vs. Vcc fSYS = 32.768 kHz internal RC 40 85 °C -40 °C 25 °C 35 30 ICC [uA] 25 20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-12. Idle Supply Current vs. Vcc fSYS = 2.0 MHz internal RC 700 -40 °C 25 °C 85 °C 600 ICC [uA] 500 400 300 200 100 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-13. Idle Supply Current vs. Vcc fSYS = 32 MHz internal RC prescaled to 8 MHz 3.5 -40 °C 25 °C 85 °C 3.0 ICC [mA] 2.5 2.0 1.5 1.0 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-14. Idle Supply Current vs. Vcc fSYS = 32 MHz internal RC 10 -40 °C 25 °C 85 °C ICC [mA] 8 6 4 2 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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XMEGA A3B 35.3 Power-down Supply Current Figure 35-15. Power-down Supply Current vs. Temperature 2 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 1.8 1.6 ICC [uA] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 35-16. Power-down Supply Current vs. Temperature With WDT and sampled BOD enabled. 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 3 2.5 ICC [uA] 2 1.5 1 0.
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XMEGA A3B 35.4 Power-save Supply Current Figure 35-17. Power-save Supply Current vs. Temperature With WDT, sampled BOD and RTC from ULP enabled 3 3.3 V 3.0 V 2.7 V 1.8 V 2.2 V 2.5 ICC [uA] 2 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 35.5 Pin Pull-up Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 100 IRESET [uA] 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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XMEGA A3B Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.0V 160 140 IRESET [uA] 120 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 VRESET [V] Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.3V 180 160 140 IRESET [uA] 120 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.
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XMEGA A3B 35.6 Pin Output Voltage vs. Sink/Source Current Figure 35-21. I/O Pin Output Voltage vs. Source Current Vcc = 1.8V 2 -40 °C 25 °C 85 °C 1.8 1.6 VPIN [V] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 35-22. I/O Pin Output Voltage vs. Source Current Vcc = 3.0V 3.5 -40 °C 25 °C 85 °C 3 VPIN [V] 2.5 2 1.5 1 0.
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XMEGA A3B Figure 35-23. I/O Pin Output Voltage vs. Source Current Vcc = 3.3V 3.5 -40 °C 25 °C 85 °C 3 VPIN [V] 2.5 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 35-24. I/O Pin Output Voltage vs. Sink Current Vcc = 1.8V 85°C 25°C 1.8 1.6 1.4 VPIN [V] 1.2 -40 °C 1 0.8 0.6 0.4 0.
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XMEGA A3B Figure 35-25. I/O Pin Output Voltage vs. Sink Current Vcc = 3.0V 0.7 85 °C 0.6 25 °C -40 °C VPIN [V] 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 35-26. I/O Pin Output Voltage vs. Sink Current Vcc = 3.3V VPIN [V] 0.7 0.6 85 °C 0.5 25 °C -40 °C 0.4 0.3 0.2 0.
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XMEGA A3B 35.7 Pin Thresholds and Hysteresis Figure 35-27. I/O Pin Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” 2.5 -40 °C 25 °C 85 °C Vthreshold [V] 2 1.5 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-28. I/O Pin Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” 1.8 85 °C 25 °C -40 °C 1.6 1.4 Vthreshold [V] 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-29. I/O Pin Input Hysteresis vs. VCC 0.7 0.6 Vthreshold [V] 0.5 85 °C 25 °C -40 °C 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-30. Reset Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” 1.8 -40 °C 25 °C 85 °C 1.6 VTHRESHOLD [V] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B Figure 35-31. Reset Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” 1.8 -40 °C 25 °C 85 °C 1.6 VTHRESHOLD [V] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 35.8 Bod Thresholds Figure 35-32. BOD Thresholds vs. Temperature BOD Level = 1.6V VBOT [V] 1.67 1.66 Rising Vcc 1.65 Falling Vcc 1.64 1.63 1.62 1.
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XMEGA A3B Figure 35-33. BOD Thresholds vs. Temperature BOD Level = 2.9V 3.06 3.04 Rising Vcc 3.02 VBOT [V] 3 2.98 Falling Vcc 2.96 2.94 2.92 2.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 35.9 35.9.1 Oscillators and Wake-up Time Internal 32.768 kHz Oscillator Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size T = -40 to 85C, VCC = 3V 0.80 % Step size: f [kHz] 0.65 % 0.50 % 0.35 % 0.20 % 0.
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XMEGA A3B 35.9.2 Internal 2 MHz Oscillator Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size T = -40 to 85C, VCC = 3V 0.50 % 0.40 % Step size: f [MHz] 0.30 % 0.20 % 0.10 % 0.00 % -0.10 % -0.20 % -0.30 % 0 16 32 48 64 80 96 112 128 56 64 DFLLRC2MCALA Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size T = -40 to 85C, VCC = 3V 3.00 % Step size: f [MHz] 2.50 % 2.00 % 1.50 % 1.00 % 0.50 % 0.
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XMEGA A3B 35.9.3 Internal 32 MHZ Oscillator Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size T = -40 to 85C, VCC = 3V 0.60 % 0.50 % Step size: f [MHz] 0.40 % 0.30 % 0.20 % 0.10 % 0.00 % -0.10 % -0.20 % 0 16 32 48 64 80 96 112 128 56 64 DFLLRC32MCALA Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size T = -40 to 85C, VCC = 3V 3.00 % Step size: f [MHz] 2.50 % 2.00 % 1.50 % 1.00 % 0.50 % 0.
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XMEGA A3B 35.10 Module current consumption Figure 35-39. AC current consumption vs. Vcc Low-power Mode Module current consumption [uA] 120 85 °C 25 °C 100 -40 °C 80 60 40 20 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 35-40. Power-up current consumption vs. Vcc -40 °C 25 °C 85 °C 700 600 ICC [uA] 500 400 300 200 100 0 0.4 0.6 0.8 1 1.2 1.4 1.
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XMEGA A3B 35.11 Reset Pulsewidth Figure 35-41. Minimum Reset Pulse Width vs. Vcc 120 100 85 °C 25 °C -40 °C tRST [ns] 80 60 40 20 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 35.12 PDI Speed Figure 35-42. PDI Speed vs. Vcc 35 25 °C 30 fMAX [MHz] 25 20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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XMEGA A3B 36. Errata 36.1 36.1.1 ATxmega256A3B rev. C • • • • • • • • • • • • • • • • • • • • • • • • • • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC has increased INL error for some operating conditions ADC gain stage non-functional ADC Event on compare match non-functional Bandgap measurement with the ADC is non-functional when VCC is below 2.
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XMEGA A3B Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V VSCALE [V] 2.5 2 1.8 V 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error.
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XMEGA A3B Problem fix/Workaround None. 7. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 36-1.
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XMEGA A3B 12. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 13.
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XMEGA A3B Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 18. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual.
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XMEGA A3B 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 22. TWI Data Interrupt Flag (DIF) erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF).
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XMEGA A3B 37. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 37.2 37.3 37.4 8116J - 06/13 1. Not recommended for new designs - Use ATxmega256A3BU 1. Updated ”Errata” on page 95. 1. Updated Footnote 2 of Figure 2-1 on page 3. 2. Updated ”Features” on page 28. Event Channel 0 output on port pin 7. 3.
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XMEGA A3B 37.5 37.6 37.7 37.8 6. Updated ”Alternate Pin Functions” on page 52. 7. Updated ”Operating voltage and frequency” on page 66 by replacing SYS to CPU. 8. Replaced Table 34-3 on page 67. 9. Updated Table 34-3 on page 67, Endurance and Data Retention. 11. Updated ”PAD Characteristics” on page 70. Input hysteresis is in V and not in mV. 12. Added new table ”Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal” on page 72. 13.
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XMEGA A3B 37.9 8116B - 12/08 1. Added ”Errata” on page 95 for ATxmega256A3B rev A. 1. Initial version. 37.
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XMEGA A3B Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ..........................................
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XMEGA A3B 10.2Overview ...............................................................................................................17 10.3Clock Options ........................................................................................................18 11 Power Management and Sleep Modes ................................................. 20 11.1Features ................................................................................................................20 11.2Overview ...................
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XMEGA A3B 18.2Overview ...............................................................................................................35 19 RTC32 - 32-bit Real-Time Counter ........................................................ 36 19.1Features ................................................................................................................36 20 TWI - Two Wire Interface ....................................................................... 37 20.1Features .................................
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XMEGA A3B 29 Program and Debug Interfaces ............................................................. 49 29.1Features ................................................................................................................49 29.2Overview ...............................................................................................................49 29.3JTAG interface ......................................................................................................49 29.
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35.6Pin Output Voltage vs. Sink/Source Current .........................................................84 35.7Pin Thresholds and Hysteresis ..............................................................................87 35.8Bod Thresholds .....................................................................................................89 35.9Oscillators and Wake-up Time ..............................................................................90 35.10Module current consumption .....................
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.