Datasheet

8116J–AVR–06/2013

XMEGA A3B

Not recommended for new designs -

Use ATxmega256A3BU

12. DAC refresh may be blocked in S/H mode

If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is

done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this

will block refresh signals to the second channel.

Problem fix/Workaround

When using the DAC in S/H mode, ensure that none of the channels is running at maximum

conversion rate, or ensure that the conversion rate of both channels is high enough to not

require refresh.

13. Conversion lost on DAC channel B in event triggered mode

If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1

conversions are occasionally lost. This means that not all data-values written to the

Channel 1 data register are converted.

Problem fix/Workaround

Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-

eral clock frequency so the conversion internal never is shorter than 1.5 µs.

14. EEPROM page buffer always written when NVM DATA0 is written

If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM

page buffer.

Problem fix/Workaround

Before writing to NVM DATA0, for example when doing software CRC or flash page buffer

write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM

DATA0 when EELOAD is set.

15. Pending full asynchronous pin change interrupts will not wake the device

Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the

sleep instruction is executed, will be ignored until the device is woken from another source

or the source triggers again. This applies when entering all sleep modes where the System

Clock is stopped.

Problem fix/Workaround

None.

16. Pin configuration does not affect Analog Comparator output

The Output/Pull and inverted pin configuration does not affect the Analog Comparator

output.

Problem fix/Workaround

None for Output/Pull configuration.

For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect

positive input to the negative AC input and vice versa), or use and external inverter to

change polarity of Analog Comparator output.

17. NMI Flag for Crystal Oscillator Failure automatically cleared

NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-

cuting the NMI interrupt handler.