Datasheet

28
8116J–AVR–06/2013
XMEGA A3B
Not recommended for new designs -
Use ATxmega256A3BU
15. I/O Ports
15.1 Features
• Selectable input and output configuration for each pin individually
• Flexible pin configuration through dedicated Pin Configuration Register
• Synchronous and/or asynchronous input sensing with port interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Asynchronous wake-up from all input sensing configurations
• Two port interrupts with flexible pin masking
• Highly configurable output driver and pull settings:
– Totem-pole
– Pull-up/-down
– Wired-AND
– Wired-OR
– Bus-keeper
– Inverted I/O
• Optional Slew rate control
• Configuration of multiple pins in a single operation
• Read-Modify-Write (RMW) support
• Toggle/clear/set registers for Output and Direction registers
• Clock output on port pin
• Event Channel 0 output on port pin 7
• Mapping of port registers (virtual ports) into bit accessible I/O memory space
15.2 Overview
The XMEGA A3B devices have flexible General Purpose I/O Ports. A port consists of up to 8
pins, ranging from pin 0 to pin 7. The ports implement several functions, including synchro-
nous/asynchronous input sensing, pin change interrupts and configurable output settings. All
functions are individual per pin, but several pins may be configured in a single operation.
15.3 I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate func-
tions. The port pins also have configurable slew rate limitation to reduce electromagnetic
emission.