Datasheet

13
8116J–AVR–06/2013
XMEGA A3B
Not recommended for new designs -
Use ATxmega256A3BU
7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) give the page number and the least significant address bits (FWORD)
give the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Table 7-3 on page 13 shows EEPROM memory organization for the XMEGA A3B devices.
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give
the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of Bytes and Pages in the EEPROM.
Devices Flash Size Page Size FWORD FPAGE Application Boot
(words) Size No of Pages Size No of Pages
ATxmega256A3B 256 KB + 8 KB 256 Z[8:1] Z[18:9] 256 KB 512 8 KB 16
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes)
ATxmega256A3B 4 KB 32 ADDR[4:0] ADDR[11:5] 128