Datasheet

11
8116J–AVR–06/2013
XMEGA A3B
Not recommended for new designs -
Use ATxmega256A3BU
7.4.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3B is shown in the
”Peripheral Module Address Map” on page 57.
7.4.2 SRAM Data Memory
The XMEGA A3B devices have internal SRAM memory for data storage.
7.4.3 EEPROM Data Memory
The XMEGA A3B devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
1000
EEPROM
(4 KB)
1FFF
2000
Internal SRAM
(16 KB)
5FFF
Figure 7-2. Data Memory Map (Hexadecimal address)