Datasheet

100
8116J–AVR–06/2013
XMEGA A3B
Not recommended for new designs -
Use ATxmega256A3BU
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
22. TWI Data Interrupt Flag (DIF) erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Pending asynchronous RTC32-interrupts will not wake up device
Asynchronous Interrupts from the 32-bit Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
25. XOSCDFD can not be cleared by writing one to bit location
The Crystal Oscillator Failure Detection Flag (XOSCFDF) can not be cleared by writing one
to its bit location. The bit can only be cleared by issuing a reset to the VBAT domain.
Problem fix/Workaround
None.
26. Maximum operating frequency below 1.76V is 8 MHz
To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz.
Problem fix/Workaround
None, avoid running the device outside this frequency and voltage limitation.