Datasheet

5
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
3.1 Block Diagram
Figure 3-1. XMEGA A3 Block Diagram
PE[0..7]
PORT E (8)
TCE0:1
USARTE0:1
TWIE
SPIE
TCF0
USARTF0
PORT F (8)
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
DMA
Controller
BUS
Controller
SRAM
ADCA
ACA
DACB
ADCB
ACB
OCD
PDI
CPU
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
Flash EEPROM
NVM Controller
DES
AES
IRCOM
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PORT R (2)
XTAL1
XTAL2
PR[0..1]
PORT D (8)
TCD0:1
USARTD0:1
SPID
TOSC1
TOSC2
EVENT ROUTING NETWORK
PF[0..7]
To Clock
Generato
r
Int. Ref.
AREFA
AREFB
Tempref
VCC/10