Datasheet

11
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3
0
I/O Registers
(4 KB)
0
I/O Registers
(4 KB)
0
I/O Registers
(4 KB)
FFF FFF FFF
1000
EEPROM
(2 KB)
1000
EEPROM
(2 KB)
1000
EEPROM
(2 KB)
17FF 17FF 17FF
RESERVED RESERVED RESERVED
2000
Internal SRAM
(16 KB)
2000
Internal SRAM
(8 KB)
2000
Internal SRAM
(4 KB)
5FFF 3FFF 2FFF
Byte Address ATxmega256A3
0
I/O Registers
(4 KB)
FFF
1000
EEPROM
(4 KB)
1FFF
2000
Internal SRAM
(16 KB)
5FFF