Datasheet

78XMEGA E5 [DATASHEET]
Atmel-8153H–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–07/2014
Table 36-8. Clock and timing.
Table 36-9. Accuracy characteristics.
Vin Input range 0 V
REF
V
Vin Conversion range Differential mode, Vinp - Vinn -0.95*V
REF
0.95*V
REF
V
Vin Conversion range Single ended unsigned mode, Vinp -0.05*V
REF
0.95*V
REF
V
Symbol Parameter Condition Min. Typ. Max. Units
Clk
ADC
ADC Clock frequency
Maximum is 1/4 of Peripheral clock
frequency
100 1800
kHz
Measuring internal signals 125
f
ClkADC
Sample rate 16 300 ksps
f
ADC
Sample rate
Current limitation (CURRLIMIT) off 16 300
ksps
CURRLIMIT = LOW 250
CURRLIMIT = MEDIUM 150
CURRLIMIT = HIGH 50
Sampling Time 1/2 Clk
ADC
cycle 0.25 5 µs
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
6 10
Clk
ADC
cycles
Start-up time ADC clock cycles 12 24
Clk
ADC
cycles
ADC settling time After changing reference or input mode 7 7
Clk
ADC
cycles
Symbol Parameter Condition Min. Typ. Max. Units
Symbol Parameter Condition
(2)
Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 8 12 12
BitsSingle ended signed 7 11 11
Single ended unsigned 8 12 12
INL
(1)
Integral non-linearity
Differential mode
16kSPS, VREF = 3V 1
lsb
16kSPS, VREF = 1V 2
300kSPS, VREF = 3V 1
300kSPS, VREF = 1V 2
Single ended
unsigned mode
16kSPS, VREF = 3.0V 1 1.5
16kSPS, VREF = 1.0V 2 3