Datasheet

49XMEGA E5 [DATASHEET]
Atmel-8153H–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–07/2014
lines (TXD/RXD) data encoding/decoding will be possible. Connecting together the LUT units, RS Latch or any
combinatorial logic between two operands or three inputs can be enabled.
The LUT works in all sleep modes. Combined with event system and one I/O pin, the LUT can wake-up the system if, and
only if, condition on up to 3 input pins is true.
A block diagram of the programmable logic unit with extensions and closely related peripheral modules (in grey) is shown
in Figure 26-1.
Figure 26-1. XMEGA custom logic module and closely related peripherals.
Interrupts
Interconnect Array
Interconnect Array
Glue Logic
LUT1
LUT0
Truth
Table
Truth
Table
D
Q
D
Q
G
Timer/Counter
BTC0
8-bit T/C
Normal
Capture
PWM
One Shot
Periph.Counter
BTC1
One Shot
PWM
Capture
Normal
Periph.Counter
8-bit T/C
Control Registers
Event
System
Port
Pins
USART