Datasheet

20XMEGA E5 [DATASHEET]
Atmel-8153H–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–07/2014
11. System Clock and Clock options
11.1 Features
z Fast start-up time
z Safe run-time clock switching
z Internal Oscillators:
z 32MHz run-time calibrated and tuneable oscillator
z 8MHz calibrated oscillator with 2MHz output option and fast start-up
z 32.768kHz calibrated oscillator
z 32kHz Ultra Low Power (ULP) oscillator with 1kHz output
z External clock options
z 0.4 - 16MHz Crystal Oscillator
z 32kHz crystal oscillator with digital correction
z External clock input in selectable pin location
z PLL with 20 - 128MHz output frequency
z Internal and external clock options and 1 to 31x multiplication
z Lock detector
z Clock Prescalers with 1x to 2048x division
z Fast peripheral clocks running at 2 and 4 times the CPU clock frequency
z Automatic Run-Time Calibration of the 32MHz internal oscillator
z External oscillator and PLL lock failure detection with optional non maskable interrupt
11.2 Overview
Atmel AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift
over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch
to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system
clock source and prescalers can be changed from software at any time.
Figure 11-1 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need to be
active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction
registers, as described in “Power Management and Sleep Modes” on page 23.