Datasheet
Table Of Contents
- Features
- 1. Ordering Information
- 2. Pinout/Block Diagram
- 3. Overview
- 4. Resources
- 5. Capacitive touch sensing
- 6. AVR CPU
- 7. Memories
- 8. Event System
- 9. System Clock and Clock options
- 9.1 Features
- 9.2 Overview
- 9.3 Clock Sources
- 9.3.1 32kHz Ultra Low Power Internal Oscillator
- 9.3.2 32.768kHz Calibrated Internal Oscillator
- 9.3.3 32.768kHz Crystal Oscillator
- 9.3.4 0.4 - 16MHz Crystal Oscillator
- 9.3.5 2MHz Run-time Calibrated Internal Oscillator
- 9.3.6 32MHz Run-time Calibrated Internal Oscillator
- 9.3.7 External Clock Sources
- 9.3.8 PLL with 1x-31x Multiplication Factor
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. WDT – Watchdog Timer
- 13. Interrupts and Programmable Multilevel Interrupt Controller
- 14. I/O Ports
- 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
- 16. TC2 – Timer/Counter Type 2
- 17. AWeX – Advanced Waveform Extension
- 18. Hi-Res – High Resolution Extension
- 19. RTC – 16-bit Real-Time Counter
- 20. USB – Universal Serial Bus Interface
- 21. TWI – Two-Wire Interface
- 22. SPI – Serial Peripheral Interface
- 23. USART
- 24. IRCOM – IR Communication Module
- 25. CRC – Cyclic Redundancy Check Generator
- 26. ADC – 12-bit Analog to Digital Converter
- 27. AC – Analog Comparator
- 28. Programming and Debugging
- 29. Pinout and Pin Functions
- 30. Peripheral Module Address Map
- 31. Instruction Set Summary
- 32. Packaging information
- 33. Electrical Characteristics TBD
- 34. Typical Characteristics TBD
- 35. Errata
- 36. Datasheet Revision History
- Table of Contents
60
8493A–AVR–02/12
XMEGA C4
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
←
←
Y - 1
(Y)
None 2
(1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
(1)(2)
LD Rd, Z Load Indirect Rd ← (Z) None 1
(1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
←
←
(Z),
Z+1
None 1
(1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
←
←
Z - 1,
(Z)
None 2
(1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
(1)(2)
STS k, Rr Store Direct to Data Space (k) ← Rd None 2
(1)
ST X, Rr Store Indirect (X) ← Rr None 1
(1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
←
←
Rr,
X + 1
None 1
(1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
←
←
X - 1,
Rr
None 2
(1)
ST Y, Rr Store Indirect (Y) ← Rr None 1
(1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
←
←
Rr,
Y + 1
None 1
(1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
←
←
Y - 1,
Rr
None 2
(1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2
(1)
ST Z, Rr Store Indirect (Z) ← Rr None 1
(1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
←
←
Rr
Z + 1
None 1
(1)
ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None 2
(1)
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
(1)
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
←
←
(Z),
Z + 1
None 3
ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
None 3
SPM Store Program Memory (RAMPZ:Z) ← R1:R0 None -
SPM Z+ Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
None -
IN Rd, A In From I/O Location Rd ← I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 1
(1)
POP Rd Pop Register from Stack Rd ← STACK None 2
(1)
XCH Z, Rd Exchange RAM location Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Te mp
None 2
LAS Z, Rd Load and Set RAM location Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Te m p v ( Z )
None 2
LAC Z, Rd Load and Clear RAM location Temp
Rd
(Z)
←
←
←
Rd,
(Z),
($FFh – Rd) • (Z)
None 2
Mnemonics Operands Description Operation Flags #Clocks