Datasheet
Table Of Contents
- Features
- 1. Ordering Information
- 2. Pinout/Block Diagram
- 3. Overview
- 4. Resources
- 5. Capacitive touch sensing
- 6. AVR CPU
- 7. Memories
- 8. Event System
- 9. System Clock and Clock options
- 9.1 Features
- 9.2 Overview
- 9.3 Clock Sources
- 9.3.1 32kHz Ultra Low Power Internal Oscillator
- 9.3.2 32.768kHz Calibrated Internal Oscillator
- 9.3.3 32.768kHz Crystal Oscillator
- 9.3.4 0.4 - 16MHz Crystal Oscillator
- 9.3.5 2MHz Run-time Calibrated Internal Oscillator
- 9.3.6 32MHz Run-time Calibrated Internal Oscillator
- 9.3.7 External Clock Sources
- 9.3.8 PLL with 1x-31x Multiplication Factor
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. WDT – Watchdog Timer
- 13. Interrupts and Programmable Multilevel Interrupt Controller
- 14. I/O Ports
- 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
- 16. TC2 – Timer/Counter Type 2
- 17. AWeX – Advanced Waveform Extension
- 18. Hi-Res – High Resolution Extension
- 19. RTC – 16-bit Real-Time Counter
- 20. USB – Universal Serial Bus Interface
- 21. TWI – Two-Wire Interface
- 22. SPI – Serial Peripheral Interface
- 23. USART
- 24. IRCOM – IR Communication Module
- 25. CRC – Cyclic Redundancy Check Generator
- 26. ADC – 12-bit Analog to Digital Converter
- 27. AC – Analog Comparator
- 28. Programming and Debugging
- 29. Pinout and Pin Functions
- 30. Peripheral Module Address Map
- 31. Instruction Set Summary
- 32. Packaging information
- 33. Electrical Characteristics TBD
- 34. Typical Characteristics TBD
- 35. Errata
- 36. Datasheet Revision History
- Table of Contents
14
8493A–AVR–02/12
XMEGA C4
memory section, see Figure 7-2. To simplify development, I/O Memory, EEPROM and SRAM
will always have the same start addresses for all Atmel AVR XMEGA devices.
7.6 EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate
data space (default) or memory mapped and accessed in normal data space. The EEPROM
supports both byte and page access. Memory mapped EEPROM allows highly efficient
EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using
load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules is shown in the ”Peripheral Module
Address Map” on page 57.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
7.8 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle,
and three cycles are required for read. For burst read, new data are available every second
cycle. Refer to the instruction summary for more details on instructions and instruction timing.
Figure 7-2. Data memory map (hexadecimal address).
Byte Address ATxmega16C4 Byte Address ATxmega128C3
0
I/O Registers
(4KB)
0
I/O Registers
(4KB)
FFF FFF
1000
EEPROM
(1K)
1000
EEPROM
(1K)
17FF 13FF
RESERVED RESERVED
2000
Internal SRAM
(2K)
2000
Internal SRAM
(4K)
2FFF 27FF