Datasheet
Table Of Contents
- Features
- 1. Ordering Information
- 2. Pinout/Block Diagram
- 3. Overview
- 4. Resources
- 5. Capacitive touch sensing
- 6. AVR CPU
- 7. Memories
- 8. Event System
- 9. System Clock and Clock options
- 9.1 Features
- 9.2 Overview
- 9.3 Clock Sources
- 9.3.1 32kHz Ultra Low Power Internal Oscillator
- 9.3.2 32.768kHz Calibrated Internal Oscillator
- 9.3.3 32.768kHz Crystal Oscillator
- 9.3.4 0.4 - 16MHz Crystal Oscillator
- 9.3.5 2MHz Run-time Calibrated Internal Oscillator
- 9.3.6 32MHz Run-time Calibrated Internal Oscillator
- 9.3.7 External Clock Sources
- 9.3.8 PLL with 1x-31x Multiplication Factor
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. WDT – Watchdog Timer
- 13. Interrupts and Programmable Multilevel Interrupt Controller
- 14. I/O Ports
- 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
- 16. TC2 – Timer/Counter Type 2
- 17. AWeX – Advanced Waveform Extension
- 18. Hi-Res – High Resolution Extension
- 19. RTC – 16-bit Real-Time Counter
- 20. USB – Universal Serial Bus Interface
- 21. TWI – Two-Wire Interface
- 22. SPI – Serial Peripheral Interface
- 23. USART
- 24. IRCOM – IR Communication Module
- 25. CRC – Cyclic Redundancy Check Generator
- 26. ADC – 12-bit Analog to Digital Converter
- 27. AC – Analog Comparator
- 28. Programming and Debugging
- 29. Pinout and Pin Functions
- 30. Peripheral Module Address Map
- 31. Instruction Set Summary
- 32. Packaging information
- 33. Electrical Characteristics TBD
- 34. Typical Characteristics TBD
- 35. Errata
- 36. Datasheet Revision History
- Table of Contents
28
8493A–AVR–02/12
XMEGA C4
14. I/O Ports
14.1 Features
• 34 general purpose input and output pins with individual configuration
• Output driver with configurable driver and pull settings:
– Totem-pole
– Wired-AND
–Wired-OR
– Bus-keeper
– Inverted I/O
• Input with synchronous and/or asynchronous sensing with interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
• Optional slew rate control
• Asynchronous pin change sensing that can wake the device from all sleep modes
• Two port interrupts with pin masking per I/O port
• Efficient and safe access to port pins
– Hardware read-modify-write through dedicated toggle/clear/set registers
– Configuration of multiple pins in a single operation
– Mapping of port registers into bit-accessible I/O memory space
• Peripheral clocks output on port pin
• Real-time counter clock output to port pin
• Event channels can be output on port pin
• Remapping of digital peripheral pin functions
– Selectable USART, SPI, and timer/counter input/output pin locations
14.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or
output with configurable driver and pull settings. They also implement synchronous and asyn-
chronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin-change sensing means that a pin change can wake the device from all sleep
modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a sin-
gle operation. The pins have hardware read-modify-write (RMW) functionality for safe and
correct change of drive value and/or pull resistor configuration. The direction of one port pin can
be changed without unintentionally changing the direction of any other pin.
The port pin configuration also controls input and output selection of other device functions. It is
possible to have both the peripheral clock and the real-time clock output to a port pin, and avail-
able for external use. The same applies to events from the event system that can be used to
synchronize and control external functions. Other digital peripherals, such as USART, SPI, and
timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.