Features • High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller • Nonvolatile program and data memories • • • • • – 16K - 32KBytes of In-System Self-Programmable Flash – 4KBytes Boot Code Section with Independent Lock Bits – 1KBytes EEPROM – 2K - 4KBytes Internal SRAM Peripheral features – Four-channel event system – Four 16-bit timer/counters Three timer/counters with four output compare or input capture channels One timer/counter with two output compare or input capture channels Hi
XMEGA C4 1. Ordering Information Ordering code ATxmega32C4-AU Flash (bytes) EEPROM (bytes) SRAM (bytes) 32K + 4K 1K Power supply Package (1)(2)(3) Temp.
XMEGA C4 2. Pinout/Block Diagram PA4 PA3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET_PDI PDI 43 42 41 40 39 38 37 36 35 34 Block diagram and pinout. 44 Figure 2-1.
XMEGA C4 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
XMEGA C4 3.1 Block Diagram Figure 3-1. XMEGA C4 block diagram. PR[0..1] XTAL/ TOSC1 Programming, debug, test Power Ground Digital function Analog function /Oscillators External clock /Crystal pins General Purpose I /O XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..
XMEGA C4 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • Atmel AVR XMEGA C manual • XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA C manual describes the modules and peripherals in depth.
XMEGA C4 6. AVR CPU 6.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU • • • • • • • 6.
XMEGA C4 The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
XMEGA C4 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result.
XMEGA C4 During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three.
XMEGA C4 7. Memories 7.
XMEGA C4 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.
XMEGA C4 7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
XMEGA C4 memory section, see Figure 7-2. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. Figure 7-2. Data memory map (hexadecimal address). Byte Address 0 FFF 1000 17FF ATxmega16C4 I/O Registers (4KB) EEPROM (1K) Byte Address 0 FFF 1000 13FF RESERVED 2000 2FFF 7.
XMEGA C4 7.9 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 7.10 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions.
XMEGA C4 8. Event System 8.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events • • • • 8.
XMEGA C4 Figure 8-1. Event system overview and connected peripherals. CPU / Software Event Routing Network clkPER Prescaler Real Time Counter ADC Event System Controller Timer / Counters AC USB Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum routing latency is two peripheral clock cycles.
XMEGA C4 9. System Clock and Clock options 9.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: • • • • • • 9.2 – 32MHz run-time calibrated and tuneable oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output External clock options – 0.4MHz - 16MHz crystal oscillator – 32.
XMEGA C4 Figure 9-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB System Clock Prescalers Brown-out Detector Prescaler Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32kHz Int. ULP 32.768kHz Int. OSC 32.768kHz TOSC 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 9.3 0.
XMEGA C4 9.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 9.3.2 32.
XMEGA C4 10. Power Management and Sleep Modes 10.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
XMEGA C4 10.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt. 10.3.3 Power-save Mode Power-save mode is identical to power down, with one exception.
XMEGA C4 11. System Control and Reset 11.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset – Brownout reset – PDI reset – Software reset • Asynchronous operation – No running system clock in the device is required for reset • Reset status register for reading the reset source from the application code 11.
XMEGA C4 11.4 11.4.1 Reset Sources Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V CC rises and reaches the POR threshold voltage (VPOT ), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. 11.4.
XMEGA C4 12. WDT – Watchdog Timer 12.1 Features • • • • • Issues a device reset if the timer is not reset before its timeout period Asynchronous operation from dedicated oscillator 1kHz output of the 32kHz ultra low power oscillator 11 selectable timeout periods, from 8ms to 8s Two operation modes: – Normal mode – Window mode • Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
XMEGA C4 13. Interrupts and Programmable Multilevel Interrupt Controller 13.
XMEGA C4 Table 13-1. Reset and interrupt vectors.
XMEGA C4 14. I/O Ports 14.1 Features • 34 general purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: • • • • • • • • • • 14.
XMEGA C4 14.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input).
XMEGA C4 14.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 14-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 14-6. I/O configuration - Wired-AND with optional pull-up.
XMEGA C4 14.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7. Figure 14-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.
XMEGA C4 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 15.1 Features • Five 16-bit timer/counters • • • • • • • • • • • • 15.
XMEGA C4 A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
XMEGA C4 16. TC2 – Timer/Counter Type 2 16.1 Features • Eight eight-bit timer/counters • • • • • 16.
XMEGA C4 17. AWeX – Advanced Waveform Extension 17.
XMEGA C4 18. Hi-Res – High Resolution Extension 18.1 Features • Increases waveform generator resolution up to 8x (three bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
XMEGA C4 19. RTC – 16-bit Real-Time Counter 19.1 Features • 16-bit resolution • Selectable clock source • • • • • 19.2 – 32.768kHz external crystal – External clock – 32.
XMEGA C4 20. USB – Universal Serial Bus Interface 20.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints • • • • • • • • • • • • 20.
XMEGA C4 the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
XMEGA C4 21. TWI – Two-Wire Interface 21.1 Features • Two Identical two-wire interface peripherals • Bidirectional, two-wire communication interface • • • • • • • • • 21.
XMEGA C4 It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
XMEGA C4 22. SPI – Serial Peripheral Interface 22.1 Features • • • • • • • • • 22.
XMEGA C4 23. USART 23.1 Features • Three identical USART peripherals • Full-duplex operation • Asynchronous or synchronous operation • • • • • • • 23.
XMEGA C4 PORTC has two USARTs whereas PORTD has one USART. Notation of these peripherals are USARTC0, USARTC1, and USARTD0 respectively.
XMEGA C4 24. IRCOM – IR Communication Module 24.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2Kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built-in filtering • Can be connected to and used by any USART 24.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.
XMEGA C4 25. CRC – Cyclic Redundancy Check Generator 25.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space • Integrated with flash memory, and CPU – Automatic CRC of the complete or a selectable range of the flash memory – CPU can load data to the CRC generator through the I/O interface • CRC polynomial software selectable to – CRC-16 (CRC-CCITT) – CRC-32 (IEEE 802.
XMEGA C4 26. ADC – 12-bit Analog to Digital Converter 26.1 Features • One Analog to Digital Converter (ADC) • 12-bit resolution • Up to 300 thousand samples per second • • • • • • • • 26.2 – Down to 2.3µs conversion time with 8-bit resolution – Down to 3.
XMEGA C4 Figure 26-1. ADC overview. ADC0 • • • ADC15 Compare Register ADC Internal signals ADC0 • • • ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding.
XMEGA C4 27. AC – Analog Comparator 27.1 Features • Two Analog Comparators (AC) • Selectable hysteresis • • • • • 27.
XMEGA C4 Figure 27-1. Analog comparator overview. Pin Input + AC0OUT AC0 Pin Input Hysteresis Enable Voltage Scaler ACnCTRL ACnMUXCTRL Bandgap Interrupt Mode WINCTRL Enable Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT AC1 Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 27-2. Figure 27-2. Analog comparator window function.
XMEGA C4 28. Programming and Debugging 28.
XMEGA C4 29. Pinout and Pin Functions The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 29.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 29.1.1 29.1.2 29.1.3 29.1.
XMEGA C4 29.1.5 29.1.6 29.1.
XMEGA C4 29.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 29-1.
XMEGA C4 Table 29-3. Port C - Alternate functions PIN # INTERRUPT TCC0(1)(2) AWEXC PC0 16 SYNC OC0A OC0ALS PC1 17 SYNC OC0B OC0AHS XCK0 PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 19 SYNC OC0D OC0BHS PC4 20 SYNC OC0CLS OC1A SS PC5 21 SYNC OC0CHS OC1B MOSI PC6 22 SYNC OC0DLS MISO RTCOUT SYNC OC0DHS SCK clkPER PORT C PC7 23 GND 24 VCC 25 Notes: 1. 2. 3. 4. 5. 6.
XMEGA C4 Table 29-5. PORT E Port E - Alternate functions PIN # INTERRUPT TCE0 PE0 36 SYNC OC0A PE1 37 SYNC OC0B XCK0 PE2 38 SYNC/ASYNC OC0C RXD0 PE3 39 SYNC OC0D TXD0 PE4 40 SYNC PE5 41 SYNC PE6 42 SYNC TOSC1 PE7 43 SYNC TOSC1 GND 44 VCC 45 Table 29-6.
XMEGA C4 30. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA C4. For complete register description and summary for each peripheral module, refer to the XMEGA C manual. Table 30-1.
XMEGA C4 31.
XMEGA C4 Mnemonics Operands Description CALL k call Subroutine PC ← RET Subroutine Return PC RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate Operation Flags #Clocks k None 3 / 4 (1) ← STACK None 4 / 5 (1) PC ← STACK I 4 / 5 (1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Regist
XMEGA C4 Mnemonics Operands Description Flags #Clocks LD Rd, -Y Load Indirect and Pre-Decrement Y Rd ← ← Y-1 (Y) None 2 (1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 (1)(2) LD Rd, Z Load Indirect Rd ← (Z) None 1 (1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z ← ← (Z), Z+1 None 1 (1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd ← ← Z - 1, (Z) None 2 (1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 (
XMEGA C4 Mnemonics Operands Description LAT Z, Rd Load and Toggle RAM location Operation Flags #Clocks Temp Rd (Z) ← ← ← Rd, (Z), Temp ⊕ (Z) None 2 Rd(n+1) Rd(0) C ← ← ← Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C ← ← ← Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C ← ← ← C, Rd(n), Rd(7) Z,C,N,V,H 1 Rd(7) Rd(n) C ← ← ← C, Rd(n+1), Rd(0) Z,C,N,V 1 Bit and bit-test instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd
XMEGA C4 32. Packaging information 32.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
XMEGA C4 32.2 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 Option C K b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1.
XMEGA C4 33.
XMEGA C4 34.
XMEGA C4 35. Errata 35.1 35.1.1 ATxmega32C4 rev. H No known errata 35.2 35.2.1 ATxmega16C4 rev.
XMEGA C4 36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 8493A – 02/12 1. Initial revision.
XMEGA C4 Table of Contents Features ..................................................................................................... 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 3.1Block Diagram ............................
XMEGA C4 9 System Clock and Clock options ......................................................... 18 9.1Features ..................................................................................................................18 9.2Overview .................................................................................................................18 9.3Clock Sources .........................................................................................................
XMEGA C4 17.1Features ................................................................................................................35 17.2Overview ...............................................................................................................35 18 Hi-Res – High Resolution Extension .................................................... 36 18.1Features ................................................................................................................36 18.2Overview ............
XMEGA C4 28 Programming and Debugging .............................................................. 51 28.1Features ................................................................................................................51 28.2Overview ...............................................................................................................51 29 Pinout and Pin Functions ...................................................................... 52 29.1Alternate Pin Function Description ...........
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