Datasheet

XMEGA A4U [DATASHEET]
Atmel-8387G-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_03/2014
36
17. TC2 - Timer/Counter Type 2
17.1 Features
 Six eight-bit timer/counters
 Three Low-byte timer/counter
 Three High-byte timer/counter
 Up to eight compare channels in each Timer/Counter 2
 Four compare channels for the low-byte timer/counter
 Four compare channels for the high-byte timer/counter
 Waveform generation
 Single slope pulse width modulation
 Timer underflow interrupts/events
 One compare match interrupt/event per compare channel for the low-byte timer/counter
 Can be used with the event system for count control
 Can be used to trigger DMA transactions
17.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width
modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a
high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte
timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to
generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock
source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with
optional prescaling, or from the event system. The counters are always counting down.
PORTC, and PORTD each has one Timer/Counter 2.
Notation of these are TCC2 (Time/Counter C2) and TCD2, respectively.