Datasheet

6
8069R–AVR–06/2013
XMEGA A4
Not recommended for new designs -
Use XMEGA A4U series
3.1 Block Diagram
Figure 3-1. XMEGA A4 Block Diagram
PE[0..3]
PORT E (4)
TCE0
USARTE0
TWIE
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (4)
DMA
Controller
BUS
Controller
SRAM
ADCA
ACA
DACB
OCD
PDI
CPU
PA[0..7]
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
PDI_DATA
RESET/
PDI_CLK
Sleep
Controller
Flash EEPROM
NVM Controller
DES
AES
IRCOM
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PORT R (2)
XTAL1/
TOSC1
XTAL2/
TOSC2
PR[0..1]
PORT D (8)
TCD0:1
USARTD0:1
SPID
EVENT ROUTING NETWORK
PB[0..3]
Int. Ref.
AREFA
AREFB
Tempref
VCC/10