Datasheet

42
8069R–AVR–06/2013
XMEGA A4
Not recommended for new designs -
Use XMEGA A4U series
Figure 25-1.
ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit resolution, reducing the minimum conversion time
(propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit resolution.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
ADC
Channel A
Register
Channel B
Register
Channel C
Register
Channel D
Register
Pin inputsPin inputs
1-64 X
Internal inputs
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
Event
Trigger
Configuration
Reference selection