Datasheet

12
8069R–AVR–06/2013
XMEGA A4
Not recommended for new designs -
Use XMEGA A4U series
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 12. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
7.4.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A4 is shown in the ”Periph-
eral Module Address Map” on page 53.
7.4.2 SRAM Data Memory
The XMEGA A4 devices have internal SRAM memory for data storage.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega64A4 Byte Address ATxmega32A4 Byte Address ATxmega16A4
0
I/O Registers
(4 KB)
0
I/O Registers
(4 KB)
0
I/O Registers
(4 KB)
FFF FFF FFF
1000
EEPROM
(2 KB)
1000
EEPROM
(1 KB)
1000
EEPROM
(1 KB)
17FF 13FF 13FF
RESERVED RESERVED RESERVED
2000
Internal SRAM
(4 KB)
2000
Internal SRAM
(4 KB)
2000
Internal SRAM
(2 KB)
2FFF 2FFF 27FF
Byte Address ATxmega128A4
0
I/O Registers
(4 KB)
FFF
1000
EEPROM
(2 KB)
17FF
RESERVED
2000
Internal SRAM
(8 KB)
3FFF