Datasheet

17
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
Table 7-2. Number of words and pages in the flash TBD.
Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or
one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address
register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number
and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of bytes and pages in the EEPROM.
Devices PC size Flash size Page size FWORD FPAGE Application Boot
[bits] [bytes] [words] Size
No. of
pages
Size
No. of
pages
ATxmega32D3 15 32K + 4K 128 Z[7:1] Z[15:7] 32K 128 4K 16
ATxmega64D3 16 64K + 4K 128 Z[7:1] Z[16:9] 64K 256 4K 16
ATxmega128D3 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192D3 17 192K + 8K 256 Z[8:1] Z[17:9] 192K 384 8K 16
ATxmega256D3 18 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
ATxmega384D3 18 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16
Devices EEPROM Page size E2BYTE E2PAGE No. of pages
size [bytes]
ATxmega32D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega64D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256D3 4K 32 ADDR[4:0] ADDR[11:5] 128
ATxmega384D3 4K 32 ADDR[4:0] ADDR[11:5] 128