Datasheet

176
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
32.6.15 Two-wire interface characteristics
Table 32-174 on page 176 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 32-42.
Figure 32-42. Two-wire interface bus timing.
Table 32-174. Two-wire interface characteristics.
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
Symbol Parameter Condition Min. Typ. Max. Units
V
IH
Input high voltage 0.7V
CC
V
CC
+ 0.5
V
V
IL
Input low voltage -0.5 0.3V
CC
V
hys
Hysteresis of Schmitt trigger inputs 0.05V
CC
(1)
V
OL
Output low voltage 3mA, sink current 0 0.4
t
r
Rise time for both SDA and SCL 20 + 0.1C
b
(1)(2)
300
nst
of
Output fall time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(2)
20 + 0.1C
b
(1)(2)
250
t
SP
Spikes suppressed by input filter 0 50
I
I
Input current for each I/O pin 0.1V
CC
< V
I
< 0.9V
CC
-10 10 µA
C
I
Capacitance for each I/O pin 10 pF
f
SCL
SCL clock frequency f
PER
(3)
> max(10f
SCL
, 250kHz) 0 400 kHz
R
P
Value of pull-up resistor
f
SCL
 100kHz

f
SCL
> 100kHz
t
HD;STA
Hold time (repeated) START condition
f
SCL
 100kHz 4.0
µs
f
SCL
> 100kHz 0.6
t
LOW
Low period of SCL clock
f
SCL
 100kHz 4.7
f
SCL
> 100kHz 1.3
t
HIGH
High period of SCL clock
f
SCL
 100kHz 4.0
f
SCL
> 100kHz 0.6
t
SU;STA
Set-up time for a repeated START
condition
f
SCL
 100kHz 4.7
f
SCL
> 100kHz 0.6
V
CC
0.4V–
3mA
--------------------------- -
100ns
C
b
-------------- -
300ns
C
b
-------------- -