Datasheet

117
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
32.3.14 SPI characteristics
Figure 32-19.SPI timing requirements in master mode.
Figure 32-20.SPI timing requirements in slave mode.
MSB LSB
MSB LSB
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data output)
MISO
(Data input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
MSB LSB
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data output)
MOSI
(Data input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS