Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 (9x9) 8/16-Bit 32 MHz I/O number 36

8074D–AVR–08/2013

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 64K - 128KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 2KBytes EEPROM

 4K - 8KBytes internal SRAM

 Peripheral Features

 Two-channel DMA controller

 Four-channel event system

 Two 16-bit timer/counters

 One timer/counters with 4 output compare or input capture channels

 One timer/counter with 2 output compare or input capture channels

 High resolution extensions one timer/counter

 Advanced waveform extension (AWeX) on one timer/counter

 Split mode on two timer/counters

 One USB device interface

 USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant

 32 Endpoints with full configuration flexibility

 One USARTs with IrDA support for one USART

 AES and DES crypto engine

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE

802.3) generator

 One two-wire interface with dual address match (I

C and SMBus compatible)

 One serial peripheral interface (SPI)

 16-bit Real Time Counter (RTC) with separate oscillator

 Liquid Crystal Display

 Up to 4x25 segment driver

 Built in contrast control

 ASCII character mapping

 Flexible SWAP of segment and common terminals buses

 One eight-channel, 12-bit, 300 thousand SPS Analog to Digital Converters

 Two Analog Comparators with window compare function, and current source

feature

 External interrupts on all General Purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interfaces

 JTAG (IEEE 1149.1 Compliant) interface, including boundary scan

 PDI (Program and Debug Interface)

 I/O and Packages

 36 Programmable I/O pins

 64-lead TQFP

 64-pad QFN

 64-pad DRQFN

 Operating Voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA B3 Microcontroller

ATxmega128B3 / ATxmega64B3

Summary of content (142 pages)

PAGE 1
8/16-bit Atmel XMEGA B3 Microcontroller ATxmega128B3 / ATxmega64B3 Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories          64K - 128KBytes of in-system self-programmable flash 4K - 8KBytes boot section 2KBytes EEPROM 4K - 8KBytes internal SRAM Peripheral Features  Two-channel DMA controller  Four-channel event system  Two 16-bit timer/counters  One timer/counters with 4 output compare or input capture channels  O
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1. Ordering Information Flash (Bytes) EEPROM (Bytes) SRAM (Bytes) 128K + 8K 2K 8K 128K + 8K 2K 8K 128K + 8K 2K 8K 128K + 8K 2K 8K 128K + 8K 2K 8K 128K + 8K 2K 8K 64K + 4K 2K 4K ATxmega64B3-AUR 64K + 4K 2K 4K ATxmega64B3-MH 64K + 4K 2K 4K ATxmega64B3-MHR(4) 64K + 4K 2K 4K Ordering Code ATxmega128B3-AU Speed (MHz) Power Supply Package(1)(2)(3) Temp 64A ATxmega128B3-AUR (4) ATxmega128B3-MH 32 ATxmega128B3-MHR (4) ATxmega128B3-MCU 1.6 - 3.
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2. Pinout/Block Diagram 2.1 Pinout – TQFP/QFN Figure 2-1. Block diagram and TQFP/QFN pinout 4 8 GND 9 10 PD0 11 PD1 12 PDI / RESET 13 PDI 14 1. COM2 COM1 COM0 51 50 49 AVCC 56 COM3 PB0 57 52 PB1 58 PR0 PB2 59 53 PB3 60 PR1 PB4 60 54 PB5 62 AGND PB6 63 55 PB7 64 TEMPREF Real Time Counter VREF Event Sys.
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Pinout – DRQFN Figure 2-2. DRQFN pinout for ATxmega128B3 A27 B23 A26 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A25 B22 A24 B21 A23 B20 A22 B19 A21 B18 A20 A23 B20 A22 B19 A21 B18 A20 B17 A19 B16 A18 B17 A19 B16 A18 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 A16 B15 A17 B13 A15 B14 A12 B11 A13 B12 A14 B9 A11 B10 B8 A10 A8 A25 B22 A24 B21 A17 B15 A16 B14 A15 B13 A14 B12 A13 B11 A12 B10 A11 B9 A10 B8 A9 A1 Table 2-1.
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3. Overview The Atmel® AVR® XMEGA® is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
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3.1 Block Diagram Figure 3-1. XMEGA B3 Block Diagram PR[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  XMEGA B Manual  XMEGA Application Notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA B Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   142 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
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7. Memories 7.
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7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.
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7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
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Figure 7-2. Data memory map (hexadecimal address). Byte Address ATxmega128B3 0 Byte Address ATxmega64B3 0 I/O Registers (4K) FFF I/O Registers (4KB) FFF 1000 1000 EEPROM (2K) 17FF EEPROM (2K) 17FF RESERVED 2000 RESERVED 2000 Internal SRAM (8K) 3FFF 7.6 Internal SRAM (4K) 2FFF EEPROM XMEGA B3 devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space.
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7.11 JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins. 7.12 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications.
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8. DMAC – Direct Memory Access Controller 8.
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9. Event System 9.
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Figure 9-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network ADC AC clkPER Prescaler Real Time Counter Event System Controller Timer / Counters USB Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is two peripheral clock cycles.
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10. System Clock and Clock options 10.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators:  32MHz run-time calibrated oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output   External clock options  0.4MHz - 16MHz crystal oscillator 32.
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Figure 10-1. The Clock system, clock sources and clock distribution. Real Time Counter LCD Peripherals RAM Non-Volatile Memory AVR CPU clkPER clkCPU clkPER2 clkPER4 clkRTC clkLCD USB clkUSB System Clock Prescalers Watchdog Timer Prescaler clkSYS Brown-out Detector System Clock Multiplexer (SCLKSEL) DIV32 DIV32 DIV32 RTCSRC USBSRC PLL DIV4 PLLSRC 10.3 XTAL2 0.4 – 16 MHz XTAL XTAL1 32.768 kHz TOSC TOSC2 32.768 kHz Int. OSC TOSC1 32 kHz Int. ULP 32 MHz Int. Osc 2 MHz Int.
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC and for LCD. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency.
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11. Power Management and Sleep Modes 11.1 Features  Power management for adjusting power consumption and functions  Five sleep modes  Idle Power down  Power save  Standby  Extended standby   Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the XMEGA microcontroller to stop unused modules to save power.
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11.3.3 Power-save Mode Power-save mode is identical to power down, with two exceptions: 1. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 2. If the liquid crystal display controller (LCD) is enabled, it will keep running during sleep, and the device can wake up from LCD frame completed interrupt. 11.3.
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12. System Control and Reset 12.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 12.
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12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin.
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13. WDT – Watchdog Timer 13.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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14. Interrupts and Programmable Multilevel Interrupt Controller 14.
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Program Address (Base Address) Source Interrupt Description 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x03E USB_INT_base USB on port D Interrupt base 0x046 LCD_INT_base LCD Interrupt base 0x048 AES_INT_vect AES Interrupt vector 0x04A NVM_INT_base Non-Volatile Memory Interrupt base 0x04E PORTB_INT_base Port B Interrupt base 0x052 ACB_INT_base Analog Compar
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15. I/O Ports 15.
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15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3.
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15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 15-6.
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15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 33. Figure 15-7. Input sensing system overview Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.
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16. T/C – 16-bit Timer/Counter Type 0 and 1 16.
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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins.
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17. TC2 –16-bit Timer/Counter Type 2 17.
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18. AWeX – Advanced Waveform Extension 18.
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19. Hi-Res – High Resolution Extension 19.1 Features  Increases waveform generator resolution up to 8x (3 bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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20. RTC – 16-bit Real-Time Counter 20.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator   Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 20.
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21. USB – Universal Serial Bus Interface 21.1 Features  One USB 2.0 full speed (12Mbps) and low speed (1.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB.
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22. TWI – Two Wire Interface 22.
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23. SPI – Serial Peripheral Interface 23.1 Features  One SPI peripheral  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 23.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins.
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24. USART 24.
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25. IRCOM – IR Communication Module 25.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2kbps  Selectable pulse modulation scheme  3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled   Built-in filtering  Can be connected to and used by any USART 25.2 Overview XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2kbps.
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26. AES and DES Crypto Engine 26.1 Features  Data Encryption Standard (DES) CPU instruction  Advanced Encryption Standard (AES) crypto module  DES Instruction  Encryption and decryption DES supported  Encryption/decryption in 16 CPU clock cycles per 8-byte block   AES crypto module  Encryption and decryption Supports 128-bit keys  Supports XOR data load mode to the state memory  Encryption/decryption in 375 clock cycles per 16-byte block  26.
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27. CRC – Cyclic Redundancy Check Generator 27.
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28. LCD - Liquid Crystal Display Controller 28.
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29. ADC – 12-bit Analog to Digital Converter 29.1 Features  One Analog to Digital Converters (ADC)  12-bit resolution  Up to 300 thousand samples per second   Down to 2.3µs conversion time with 8-bit resolution Down to 3.
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Figure 29-1. ADC overview ADC0 • • • ADC15 Compare Register ADC Internal signals ADC0 • • • ADC7 < > VINP Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding.
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30. AC – Analog Comparator 30.
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Figure 30-1. Analog comparator overview Pin Input + AC0 - Pin Input AC0OUT Hysteresis Enable Voltage Scaler ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + AC1 - Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Figure 30-2.
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31. Programming and Debugging 31.
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32. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 32.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 32.1.
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32.1.5 Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 32.1.
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32.1.
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32.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 32-1.
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Table 32-3. Port D - Alternate functions. PORT D PIN # INTERRUPT USBD GND 9 VCC 10 PD0 11 SYNC D- PD1 12 SYNC D+ Table 32-4. Program and Debug functions. PROG PIN # INTERRUPT PROG RESET 13 PDI_CLK PDI 14 PDI_DATA Table 32-5.
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LCD(1)(2) PIN # INTERRUPT(1) GPIO(1) BLINK(1) SEG5 36 SEG4 37 SEG3 38 SEG2 39 SEG1 40 BLINK SEG0 41 BLINK GND 42 VCC 43 BIAS1 44 BIAS2 45 VLCD 46 CAPL 47 CAPH 48 COM0 49 COM1 50 COM2 51 COM3 52 Notes: 1. 2. Pin mapping of all Segment terminals (SEGn) can be optionnaly swapped. Interrupt, GPIO and Blink functions will be automatically swapped. Pin mapping of all Common terminals (COMn) can be optionnaly swapped. Table 32-6. Port R- Alternate functions.
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33. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA B3. For complete register description and summary for each peripheral module, refer to the XMEGA B Manual. Table 33-1. Peripheral module address map.
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Base address Name Description 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 0x08C0 SPIC 0x08F8 IRCOM 0x0D00 LCD USART 0 on port C Serial Peripheral Interface on port C Infrared Communication Module Liquid Crystal Display XMEGA B3 [DATASHEET] 8074D–AVR–08/2013 61
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34.
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Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3 (1) call Subroutine PC  k None 3 / 4 (1) RET Subroutine Return PC  STACK None 4 / 5 (1) RETI Interrupt Return PC  STACK I 4 / 5 (1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with
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Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd  (k) None 2 (1)(2) LD Rd, X Load Indirect Rd  (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y+1 None 1 (1)(2) LD Rd, -Y Load In
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Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1 (1) Pop Register from Stack Rd  STACK None 2 (1) Z, Rd Exchange RAM location Temp Rd (Z)    Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z)    Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp R
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Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr.
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35. Packaging information 35.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
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35.2 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1.
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35.
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36. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 on page 70 under may cause permanent damage to the device.
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Figure 36-1. Maximum Frequency vs. Vcc MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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36.3 DC Characteristics Table 36-4. Current Consumption for active and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk Min T = 85°C WDT and Sampled BOD enabled, T = 25°C 150 VCC = 3.0V 320 VCC = 1.8V 350 VCC = 3.0V 700 VCC = 1.8V 650 800 1.0 1.6 10 15 VCC = 3.0V Power-save power consumption(2) mA 4.
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Symbol Parameter Power-save power consumption(2) ICC Reset power consumption Notes: 1. 2. Condition Min Typ RTC on ULP clock, WDT, sampled BOD and LCD enabled, and all pixels ON, T = 25°C VCC = 1.8V 4.6 VCC = 3.0V 5.2 RTC on 1.024kHz low power 32.768kHz TOSC, LCD enabled and all pixels ON T = 25°C VCC = 1.8V 3.9 VCC = 3.0V 4.3 RTC from low power 32.768kHz TOSC, LCD enabled and all pixels ON, T = 25°C VCC = 1.8V 4.0 VCC = 3.0V 4.5 Current through RESET pin substracted VCC = 3.
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Table 36-5. Current Consumption for modules and peripherals. Symbol Parameter Condition(1) Min Typ Max ULP oscillator 1.0 µA 32.768kHz int. oscillator 26 µA 2MHz int. oscillator 80 µA DFLL enabled with 32.768kHz int. osc. as reference 112 255 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 444 PLL Multiplication factor = 20x 316 µA 1 µA µA Watchdog Timer Continuous mode 126 Sampled mode, include ULP oscillator 1.
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Symbol Parameter Condition(1) Min Typ AC ICC DMA 615Kbps between I/O registers and SRAM USART Rx and Tx enabled, 9600 BAUD Flash memory and EEPROM programming Notes: 1. 2. 36.4 Max Units 440 µA 115 µA 9 µA 4.4 mA .All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz External clock without prescaling, T = 25°C unless other conditiond are given.
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36.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O Pin Characteristics. Symbol (1) IOH/ (2) Parameter Condition Max Units -20 20 mA VCC = 3.0 - 3.6V 0.6*VCC VCC+0.3 VCC = 2.3 - 2.7V 0.6*VCC VCC+0.3 VCC = 1.6 - 2.3V 0.6*VCC VCC+0.3 VCC = 3.0 - 3.6V -0.3 0.4*VCC VCC = 2.3 - 2.7V -0.3 0.4*VCC VCC = 1.6 - 2.3V -0.3 0.
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36.6 Liquid Crystal Display Characteristics Table 36-8. Symbol Liquid crystal display characteristics. Parameter Condition Min Typ Max SEG Segment terminal pins 0 40 COM Common terminal pins 0 4 fFrame LCD frame frequency 31.25 512 CFlying Flying capacitor Contrast 100 Contrast adjustment VLCD BIAS2 F(clkLCD)=32.768kHz LCD regulated voltages BIAS1 -0.5 RCOM Common output impedance COM0 to COM3 RSEG Segment output impedance SEG0 to SEG39(1) Notes: 1. 36.
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Symbol Parameter Condition Current limitation (CURRLIMIT) off fADC Min. Typ. 16 Max. Units 300 CURRLIMIT = LOW 250 CURRLIMIT = MEDIUM 150 CURRLIMIT = HIGH 50 Sample rate ksps Sampling Time 1/2 ClkADC cycle 0.25 5 µs Conversion time (latency) (RES+2)/2+(GAIN !=0) RES (Resolution) = 8 or 12 6 10 ClkADC cycles Start-up time ADC clock cycles 12 24 ClkADC cycles ADC settling time After changing reference or input mode 7 7 Min. Typ. Max.
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Symbol Condition(2) Parameter Min. Typ. Max. Units External reference -5 AVCC/1.6 -5 AVCC/2.0 -6 Bandgap ±10 Temperature drift 0.02 mV/K 2 mV/V mV Gain Error Differential mode Operating voltage drift External reference -8 AVCC/1.6 -8 AVCC/2.0 -8 Bandgap ±10 Temperature drift 0.03 mV/K 2 mV/V mV Single ended unsigned mode Gain Error Operating voltage drift Notes: 1. 2.
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36.8 Analog Comparator Characteristics Table 36-13. Analog comparator characteristics. Symbol Voff Ilk Parameter Condition Min. Typ. Input offset voltage 10 Input leakage current <10 Input voltage range Units mV 0.1 AC startup time Max. 50 nA AVCC- 0.1 V 50 µs Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0 mV Vhys2 Hysteresis, small VCC = 1.6V - 3.6V 12 mV Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 28 mV 30 Propagation delay VCC = 3.0V, T= 85°C 22 tdelay VCC = 1.6V - 3.
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36.10 Brownout Detection Characteristics Table 36-15. Brownout Detection Characteristics(1). Symbol Parameter Condition BOD level 0 falling Vcc T = 85C, calibrated Min Typ Max 1.5 1.6 1.72 BOD level 1 falling Vcc 1.8 BOD level 2 falling Vcc 2.0 BOD level 3 falling Vcc 2.2 BOD level 4 falling Vcc 2.4 BOD level 5 falling Vcc 2.6 BOD level 6 falling Vcc 2.8 BOD level 7 falling Vcc 3.0 Units V Continuous mode tBOD µs Sampled mode VHYST Note: 0.4 Detection time 1000 Hysteresis 1.
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36.13 Flash and EEPROM Memory Characteristics Table 36-18. Endurance and data retention. Symbol Parameter Condition Min 25°C 10K 85°C 10K 25°C 100 55°C 25 25°C 100K 85°C 100K 25°C 100 55°C 25 Typ Max Write/Erase cycles Units Cycle Flash Data retention Year Write/Erase cycles Cycle EEPROM Data retention Year Table 36-19. Programming time. Symbol Parameter Chip Erase Flash EEPROM Notes: 1. 2.
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36.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 36-21. Calibrated 2MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min DFLL can tune to this frequency over voltage and temperature 1.8 Factory calibrated frequency Factory calibration accuracy Typ Max Units 2.2 MHz 2.0 T = 85C, VCC= 3.0V User calibration accuracy MHz -1.5 1.5 % -0.2 0.2 % DFLL calibration stepsize 0.22 % 36.14.
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36.14.6 External Clock Characteristics Figure 36-3. External Clock Drive Waveform tCH tCH tCF tCR VIH1 VIL1 tCL tCK Table 36-25. External clock used as system clock without prescaling. Symbol Clock frequency(1) 1/tCK tCK Clock period tCH Clock high time tCL Clock low time tCR Rise time (for maximum frequency) tCF Fall time (for maximum frequency) tCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min Typ Max VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.
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Table 36-26. External clock with prescaler(1) for system clock Symbol Parameter Condition Clock Frequency(2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) tCK Notes: Min Typ VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
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Symbol Parameter Condition 44k 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k 8MHz crystal 1500 9MHz crystal 1500 8MHz crystal 2700 9MHz crystal 2700 12MHz crystal 1000 9MHz crystal 3600 12MHz crystal 1300 16MHz crystal 590 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 130
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Symbol Parameter CXTAL1 Parasitic capacitance 5.9 CXTAL2 Parasitic capacitance 8.3 Parasitic capacitance load 3.5 CLOAD Note: 1. Condition Min. Typ. Max. Units pF Numbers for negative impedance are not tested but guaranteed from design and characterization. 36.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics.
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36.15 SPI characteristics Figure 36-5. SPI interface requirements in master mode SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 36-6.
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Table 36-29. SPI Timing characteristics and requirements. Symbol Parameter Condition Min Typ Max tSCK SCK Period Master (See Table 21-4 in XMEGA B Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.
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36.16 Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7. Figure 36-7. Two-Wire Interface Bus Timing tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 36-30. Two wire serial bus characteristics. Symbol Parameter Condition Min Typ Max Units VIH Input High Voltage 0.
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Symbol Parameter tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min fSCL  100kHz 250 fSCL > 100kHz 100 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.
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37. Typical Characteristics 37.1 Current consumption 37.1.1 Active mode supply current Figure 37-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 1000 3.6V 900 800 3.0V ICC [µA] 700 2.7V 600 500 2.2V 400 1.8V 1.6V 300 200 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.6V 12 Icc[mA] 10 3.0V 2.7V 8 6 2.2V 4 1.
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Figure 37-3. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 2100 1900 -40°C 25°C 85°C ICC [uA] 1700 1500 1300 1100 900 700 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-4. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 14000 13250 -40 °C 25 °C 85 °C Icc[µA] 12500 11750 11000 10250 9500 8750 8000 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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37.1.2 Idle mode supply current Figure 37-5. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.6V 160 Icc[µA] 140 3.0V 120 2.7V 100 2.2V 80 1.8V 1.6V 60 40 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-6. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.6V 5 3.0V Icc[mA] 4 2.7V 3 2 2.2V 1 1.
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Figure 37-7. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 34.5 -40°C 33.75 85°C 33 Icc[µA] 32.25 25°C 31.5 30.75 30 29.25 28.5 27.75 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-8. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. Icc [µA] 450 425 -40°C 25°C 85°C 400 375 350 325 300 275 250 225 200 175 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-9. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5800 -40 °C 25 °C 85 °C 5300 4800 ICC [µA] 4300 3800 3300 2800 2300 1800 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 37.1.3 Power-down mode supply current Figure 37-10.Power-down mode supply current vs. Temperature. All functions disabled. 2.5 3.0 V 2.7 V 2.2 V 1.8 V 2.25 2 Icc [µA] 1.75 1.5 1.25 1 0.75 0.5 0.
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Figure 37-11.Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled. 3.5 3.0 V 2.7 V 2.2 V 1.8 V 3.25 3 Icc[µA] 2.75 2.5 2.25 2 1.75 1.5 1.25 1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] 37.2 I/O Pin Characteristics 37.2.1 Pull-up Figure 37-12.I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 80 70 IPIN [µA] 60 50 40 30 20 85°C 25°C -40°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 37-13.I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 140 120 IPIN [µA] 100 80 60 40 85°C 25°C -40°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] Figure 37-14.I/O pin pull-up resistor current vs. pin voltage. VCC = 3.3V. 160 140 IPIN [µA] 120 100 80 60 40 85°C 25°C -40°C 20 0 0 0.35 0.7 1.05 1.4 1.75 2.1 2.45 2.8 3.15 3.
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37.2.2 Output Voltage vs. Sink/Source Current Figure 37-15.I/O pin output voltage vs. source current. VCC = 1.8V. 1.3 -40°C 25°C 85°C 1.2 VPIN [V] 1.1 1 0.9 0.8 0.7 0.6 -6 -5.4 -4.8 -4.2 -3.6 -3 -2.4 -1.8 -1.2 -0.6 0 IPIN [mA] Figure 37-16.I/O pin output voltage vs. source current. VCC = 3.0V. 3.1 -40°C 25°C 85°C 2.9 2.7 VPIN[V] 2.5 2.3 2.1 1.9 1.7 1.5 1.
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Figure 37-17.I/O pin output voltage vs. source current. VCC = 3.3V. 2.5 85°C 25°C -40°C 2.25 VPIN [V] 2 1.75 1.5 1.25 1 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 37-18.I/O pin output voltage vs. sink current. VCC = 1.8V. 1.8 85°C 1.6 1.4 VPIN [V] 1.2 1 0.8 25°C 0.6 -40°C 0.4 0.
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Figure 37-19.I/O pin output voltage vs. sink current. VCC = 3.0V. 0.6 85°C 0.54 25°C 0.48 -40°C VPIN [V] 0.42 0.36 0.3 0.24 0.18 0.12 0.06 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-20.I/O pin output voltage vs. sink current. VCC = 3.3V. 0.4 85°C 0.35 25°C -40°C VPIN [V] 0.3 0.25 0.2 0.15 0.1 0.
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37.2.3 Thresholds and Hysteresis Figure 37-21.I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 25°C 85°C VTHRESHOLD [V] 1.6 1.4 1.2 1 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-22.I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.7 -40°C 25°C 85°C VTRESHOLD [V] 1.5 1.3 1.1 0.9 0.7 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-23.I/O pin input hysteresis vs. VCC. 350 VHYSTERESIS [mV] 300 250 200 150 -40°C 25°C 85°C 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] ADC Characteristics Figure 37-24.ADC INL vs. VREF. Differential signed mode, VCC = 3.6V, external reference. 2.5 2.3 2.1 1.9 INL [LSB] 37.3 1.7 1.5 1.3 -40ºC 85ºC 25ºC 1.1 0.9 0.7 0.5 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 37-25.ADC INL vs. VREF. SE Unsigned mode, VCC = 3.6V, external reference. 3.5 3.3 INL [LSB] 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 85ºC 25ºC -40ºC 0.7 0.5 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-26.ADC DNL vs. VREF. Differential signed mode, VCC = 3.6V, external reference. 2.1 2 1.9 1.8 DNL [LSB] 1.7 1.6 1.5 1.4 1.3 1.2 -40ºC 1.1 1 85ºC 0.9 25ºC 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 37-27.ADC DNL vs. VREF. SE Unsigned mode, VCC = 3.6V, external reference. 3.0 2.8 2.6 DNL [LSB] 2.4 2.2 2.0 1.8 1.6 1.4 -40ºC 25ºC 85ºC 1.2 1.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-28.ADC Offset vs. VCC. SE Unsigned mode, VREF = 1.0V, external reference. 14 85ºC 25ºC -40ºC Offset [mV] 12 10 8 6 4 2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-29.ADC Offset vs. VREF. SE Unsigned mode, VCC = 3.6V, external reference. 19 85ºC 18 17 25ºC Offset [mV] 16 15 14 -40ºC 13 12 11 10 9 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-30.ADC Offset vs. VREF. Differential signed mode, VCC = 3.6V, external reference. 10.0 9.0 Offset [mV] 8.0 85ºC 25ºC 7.0 -40ºC 6.0 5.0 4.0 3.0 2.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 37-31.ADC Offset vs. VCC. Differential signed mode, VREF = 1.0V, external reference. -3 -3.5 -4 Offset [mV] -4.5 -5 -5.5 -6 85ºC -6.5 25ºC -7 -7.5 -40ºC -8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-32.ADC Gain Error vs. VREF. Differential signed mode, external reference. -1.0 Gain Error [mV] -3.0 -5.0 -7.0 -9.0 -40ºC 25ºC 85ºC -11.0 -13.0 -15.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 37-33.ADC Gain Error vs. VREF. SE Unsigned mode, external reference. 0.0 -1.0 Gain Error [mV] -2.0 -3.0 -40ºC -4.0 -5.0 -6.0 25ºC -7.0 -8.0 85ºC -9.0 -10.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-34.ADC Gain Error vs. VCC. Differential signed mode, external reference. -3.0 -3.5 Gain Error [mV] -4.0 -4.5 -5.0 -5.5 25ºC -6.0 -40ºC -6.5 -7.0 85ºC -7.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-35.ADC Gain Error vs. VCC. SE Unsigned mode, external reference. 0 -1 Gain Error [mV] -2 -3 -4 -5 -40ºC -6 25ºC 85ºC -7 -8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-36.ADC Gain Error vs. Temperature. Differential signed mode, external reference. -5.0 -6.0 1.0V Vref Gain Error [mV] -7.0 1.5V Vref -8.0 -9.0 2.0V Vref -10.0 2.5V Vref -11.0 3.0V Vref -12.
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Figure 37-37.ADC Gain Error vs. Temperature. SE Unsigned mode, VCC = 3.6V, external reference. -40 -3.0 -30 -20 -10 0 10 20 30 40 50 60 70 80 Gain Error [mV] -4.0 -5.0 1.0V Vref -6.0 1.5V Vref -7.0 2.0V Vref -8.0 2.5V Vref 3.0V Vref -9.0 Temperature [ºC] Analog Comparator Characteristics Figure 37-38.Analog comparator hysteresis vs. VCC. High-speed mode, small hysteresis. 16 15 14 VHyst [mV] 37.4 85ºC 13 12 11 25ºC 10 9 -40ºC 8 7 6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.
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Figure 37-39.Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 32 85°C VHyst [mV] 30 28 25°C 26 24 -40°C 22 20 18 16 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-40.Analog comparator propagation delay vs. VCC. High speed mode. 34 32 tPD[ns] 30 28 26 24 22 20 85°C 18 25°C - 40°C 16 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-41.Analog comparator current consumption vs. VCC. High-speed mode. Module Consumption [µA] 290 270 85°C 250 25°C -40°C 230 210 190 170 150 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCM [V] Figure 37-42.Analog comparator voltage scaler vs. SCALEFAC. T = 25C. 4 3.6V 3.3V 3.0V 2.7V 3.5 VSCALE [V] 3 2.5 2 1.8V 1.6V 1.5 1 0.
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Figure 37-43.Analog comparator offset voltage vs. Common mode voltage. High-speed mode. 20 -40°C V OFFSET [mV] 18 16 14 25°C 12 85°C 10 8 6 4 2 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 VCC [V] Figure 37-44.Analog comparator current source vs. Calibration. VCC = 3.0V, double mode. 12 ICURRENTSOURCE [µA] 11.5 11 10.5 10 9.5 9 -40°C 25°C 85°C 8.5 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
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37.5 Internal 1.0V reference Characteristics Figure 37-45.ADC/DAC Internal 1.0V reference vs. temperature. 1.012 Bandgap Voltage [V] 1.01 1.008 1.006 1.004 1.002 1.8V 1 2.7V 3.0V 0.998 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] BOD Characteristics Figure 37-46.BOD current consumption vs. VCC. Continuous mode, BOD level = 1.6V. 150 85°C 140 25°C IccGlobal [µA] 37.6 130 -40°C 120 110 100 90 80 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 37-47.BOD current consumption vs. VCC. Sampled mode, BOD level = 1.6V. 5 4.5 85°C IccGlobal [µA] 4 3.5 3 2.5 2 1.5 25°C -40°C 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-48.BOD thresholds vs. temperature. BOD level = 1.6V. 1.626 1.624 1.622 VBOT [V] 1.62 1.618 Rising Vcc 1.616 1.614 1.612 1.61 1.608 Falling Vcc 1.606 1.
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Figure 37-49.BOD thresholds vs. temperature. BOD level = 2.2V. 2.35 2.345 2.34 Rising Vcc VBOT [V] 2.335 2.33 2.325 2.32 2.315 Falling Vcc 2.31 2.305 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-50.BOD thresholds vs. temperature. BOD level = 3.0V. 3.07 3.06 Rising Vcc VBOT [V] 3.05 3.04 3.03 3.02 Falling Vcc 3.
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External Reset Characteristics Figure 37-51.Minimum Reset pin pulse width vs. VCC. 140 130 tRST [ns] 120 110 100 85°C 90 25°C -40°C 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-52.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 70 60 50 IRESET [µA] 37.7 40 30 20 85°C 25°C -40°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 37-53.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 140 120 IRESET [µA] 100 80 60 40 85°C 25°C -40°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 37-54.Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 120 IRESET [µA] 100 80 60 40 85°C 25°C -40°C 20 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 37-55.Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 -40°C 25°C 85°C VTHRESHOLD [V] 1.6 1.4 1.2 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-56.Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.8 -40 °C 25 °C 85 °C VTHRESHOLD [V] 1.6 1.4 1.2 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.8 Oscillator Characteristics 37.8.1 32.768kHz Internal Oscillator Figure 37-57.32.768kHz internal oscillator frequency vs. temperature. 32.83 1.8V 1.6V 2.2V 3.6V 2.7V 3.0V 32.82 Frequency [kHz] 32.81 32.8 32.79 32.78 32.77 32.76 32.75 32.74 32.73 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 37-58.32.768kHz ULP internal oscillator frequency vs. temperature. 36000 35500 Frequency [Hz] 35000 34500 34000 33500 3.6V 3.0V 2.7V 1.8V 1.
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Figure 37-59.32.768kHz internal oscillator calibration step size. T = -40C to 85C, VCC = 3V. 0.01 85°C 25°C -40°C Step size: f [kHz] 0.005 0.000 -0.005 -0.01 -0.015 -0.02 -0.025 -0.03 -0.035 -0.04 -0.045 0 32 64 96 128 160 192 224 256 RC32KCAL[7..0] Figure 37-60.32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 Frequency [kHz] 50 3.0 V 45 40 35 30 25 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..
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37.8.2 2MHz Internal Oscillator Figure 37-61.2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 Frequency [MHz] 2.14 2.12 2.1 2.08 2.06 2.04 2.02 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.00 1.98 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-62.2MHz internal oscillator frequency vs. temperature. DFLL enabled. 2.006 1.6 V 2.2 V Frequency [MHz] 2.005 1.8 V 2.7 V 3.0 V 3.6 V 2.004 2.003 2.002 2.001 2.000 1.
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Figure 37-63.2MHz internal oscillator CALA calibration step size. VCC = 3V. -0.14 -0.15 85 °C -0.16 25 °C Step Error [%] -0.17 -40 °C -0.18 -0.19 -0.2 -0.21 -0.22 -0.23 -0.24 -0.25 -0.26 -0.27 0 10 20 30 40 50 60 70 80 90 100 110 120 130 DFLLRC2MCALA Figure 37-64.2MHz internal oscillator CALB calibration step size. VCC = 3V, DFLL enabled. -0.155 -0.165 85°C Step Error [%] -0.175 25°C -0.185 -40°C -0.195 -0.205 -0.215 -0.225 -0.235 -0.245 -0.
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37.8.3 32MHz Internal Oscillator Figure 37-65.32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 Frequency [MHz] 35 34.5 34 33.5 33 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 32.5 32 31.5 31 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-66.32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.08 1.8V 3.3V 2.2V Frequency [MHz] 32.06 32.04 1.6V 2.7V 32.02 3.0V 32 31.98 31.
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Figure 37-67.32MHz internal oscillator CALA calibration step size. VCC = 3.0V. -0.1 -0.12 25°C Step Error [%] -0.14 85°C -0.16 -40°C -0.18 -0.2 -0.22 -0.24 -0.26 -0.28 -0.3 0 10 20 30 40 50 60 70 80 90 100 110 120 130 DFLLRC32MCALA Figure 37-68. 32MHz internal oscillator CALB calibration step size. VCC = 3.0V, CALA = mid value. Step size: Step Error [%] 0.60 0.50 0.40 0.30 0.20 -40°C 0.10 0.00 -0.10 25°C -0.20 85°C -0.30 -0.
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Figure 37-69. 32MHz internal oscillator frequency vs. CALA calibration value. VCC = 3.0V. 56 Frequency [MHz] -40°C 54 52 25°C 50 85°C 48 46 44 42 40 38 36 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 DFLLRC32MCALA Figure 37-70.32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V, DFLL enabled.
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37.8.4 32MHz internal oscillator calibrated to 48MHz Figure 37-71. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53 Frequency [MHz] 52 51 50 49 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 48 47 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-72. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.12 1.8V 2.2V 3.6V 3.0V 1.6V 2.7V Frequency [MHz] 48.1 48.08 48.06 48.04 48.02 48 47.98 47.96 47.
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Figure 37-73. 32MHz internal oscillator CALA calibration step size. Using 48MHz calibration value from signature row, VCC = 3.0V. Step size: Step Error [%] 0.80 0.60 0.40 0.20 -40°C 85°C 0.00 -0.20 25°C -0.40 -0.60 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 37-74. 48MHz internal oscillator frequency vs. CALA calibration value. VCC = 3.0V.
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PDI characteristics Figure 37-75.Maximum PDI frequency vs. VCC. 20.5 20.0 25°C 19.5 fmin [kHz] 37.9 19.0 -40°C 18.5 18.0 85°C 17.5 17.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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37.10 LCD Characteristics Figure 37-76.ICC vs. Frame Rate 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, VCC = 1.8V, T = 25°C 11 22pF All Pixels ON 10 ICC [µA] 9 8 22pF All Pixels OFF 7 6 5 0pF All Pixels ON 4 0pF All Pixels OFF 3 32 64 96 128 160 192 224 256 Frame Rate[Hz] Figure 37-77.ICC vs. Frame Rate 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, VCC = 3.
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Figure 37-78.ICC vs. Frame Rate 0pF load 15 85 °C 13 ICC [µA] 25 °C 11 -40 °C 9 7 5 3 32 64 96 128 160 192 224 256 Frame Rate[Hz] Figure 37-79.ICC vs. Contrast 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, VCC = 1.8V 7.5 7 6.5 ICC [µA] 85°C 6 5.5 5 25°C -40°C 4.5 4 3.
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Figure 37-80.ICC vs. Contrast 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, VCC = 3.0V 7.5 7 85°C ICC [µA] 6.5 6 5.5 5 25°C 4.5 -40°C 4 3.5 3 -32 -23 -14 -5 4 13 22 31 Contrast Figure 37-81.Psave LCD LP 32Hz vs. Temperature IccModuleConsumption [µA] 3.2 3 2.8 2.6 3.6V 2.4 3.0V 2.2V 1.8V 1.6V 2.
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Figure 37-82.Psave LCD LP 32Hz vs. Temperature RTC, WDT, BOD sampled IccModuleConsumption [µA] 3.6 3.4 3.2 3.0 2.8 3.6V 2.6 3.0V 2.2V 1.8V 1.6V 2.4 2.2 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 37-83.Psave vs. Temperature RTC, WDT, BOD sampled. IccModuleConsumption [µA] 0.3 0.275 3.6V 0.25 0.225 3.0V 0.2 2.2V 0.175 0.15 -40 1.8V 1.
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38. Errata 38.1 ATxmega64B3, ATxmega128B3 38.1.1 Rev. C  Device revision number  AWeX fault protection restore is not done correct in Pattern Generation Mode 1. Device revision number is unchanged between rev. B and rev. C 2. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels.
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39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8074D – 08/2013 1. 39.2 39.3 39.4 64-pad DRQFN package option added for ATxmega128B3:  “Ordering Information” on page 2: New ordering codes for ATxmega128B3 added.  “Pinout – DRQFN” on page 4: Pinout figure and table added.  “Packaging information” : “64P2” on page 69 added.
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XMEGA B3 [DATASHEET] 8074D–AVR–08/2013 136
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 2.2 Pinout – TQFP/QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinout – DRQFN . . . . . . . . . . . . . . . . . . . . . . . . . .
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10.2 10.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 23 11.1 11.2 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Overview . . . . . . . . . . . . . . . . . . . .
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22. TWI – Two Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.1 22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
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36.1 36.2 36.3 36.4 36.5 36.6 36.7 36.8 36.9 36.10 36.11 36.12 36.13 36.14 36.15 36.16 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Wake-up time from sleep modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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XMEGA B3 [DATASHEET] 8074D–AVR–08/2013 v
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.