Datasheet

88
XMEGA B3 [DATASHEET]
8074D–AVR–08/2013
36.15 SPI characteristics
Figure 36-5. SPI interface requirements in master mode
Figure 36-6. SPI timing requirements in slave mode
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB
LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS