Datasheet

XMEGA B3 [DATASHEET]

8074D–AVR–08/2013

Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

SEV Set Two’s Complement Overflow V  1 V 1

CLV Clear Two’s Complement Overflow V  0 V 1

SET Set T in SREG T  1 T 1

CLT Clear T in SREG T  0 T 1

SEH Set Half Carry Flag in SREG H  1 H 1

CLH Clear Half Carry Flag in SREG H  0 H 1

MCU control instructions

BREAK Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Mnemonics Operands Description Operation Flags #Clocks