Datasheet

6
XMEGA B3 [DATASHEET]
8074D–AVR–08/2013
3.1 Block Diagram
Figure 3-1. XMEGA B3 Block Diagram
Power
Supervision
POR/BOD &
RESET
PORT B (8)
EVENT ROUTING NETWORK
DMA
Controller
BUS Matrix
SRAM
ADCB
ACB
OCD
PORT M (8)
PDI
SEG[16..9] /
PM[0..7]
SEG[0..8]
COM[0..3]
PB[0..7] /
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
PORT R (2)
PR[0..1]
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
PDI_DATA
RESET /
PDI_CLK
PORT B
Sleep
Controller
DES
CRC
IRCOM
PORT G (8)
SEG[24..17] /
PG[0..7]
LCD POWER[0..4]
AES
Int. Refs.
AREFB
Tempref
VCC/10
CPU
NVM Controller
Flash EEPROM
DATA BUS
XTAL2 /
TOSC2
XTAL1 /
TOSC1
Oscillator
Circuits/
Clock
Generation
PD[0..1]
PORT D (2)
USB
PORT C (8)
PC[0..7]
TCC0:1
USARTC0
TWIC
SPIC
EVENT ROUTING NETWORK
LCD
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I/O
Ground
LCDPower