Datasheet

96
XMEGA B [DATASHEET]
8291B–AVR–01/2013
7.12 Register Summary – Clock
7.13 Register Summary – Oscillator
7.14 Register Summary – DFLL32M/DFLL2M
7.15 Oscillator Failure Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL SCLKSEL[2:0] 85
+0x01 PSCTRL
PSADIV[4:0] PSBCDIV[1:0] 85
+0x02 LOCK
LOCK 87
+0x03 RTCCTRL
RTCSRC[2:0] RTCEN 87
+0x04 USBSCTRL
USBPSDIV[2:0] USBSRC[1:0] USBSEN 87
+0x05 Reserved
+0x06 Reserved
+0x07 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL PLLEN XOSCEN RC32KEN R32MEN RC2MEN 89
+0x01 STATUS
PLLRDY XOSCRDY RC32KRD R32MRDY RC2MRDY 89
+0x02 XOSCCTRL FRQRANGE[1:0] X32KLPM XOSCPW XOSCSEL[3:0] 90
XOSCSEL
+0x03 XOSCFAIL
PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN 91
+0x04 RC32KCAL RC32KCAL[7:0] 92
+0x05 PLLCTRL PLLSRC[1:0]
PLLFAC[4:0] 92
+0x06 DFLLCTRL
RC32MCREF[1:0] RC2MCREF 92
+0x07 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL ENABLE 93
+0x01 Reserved
+0x02 CALA CALA[6:0] 93
+0x03 CALB
CALB[5:0] 94
+0x04 Reserved
+0x05 COMP1 COMP[7:0] 95
+0x06 COMP2 COMP[15:8] 95
+0x07 Reserved
Offset Source Interrupt Description
0x00 OSCF_vect PLL and external oscillator failure interrupt vector (NMI)