Datasheet

92
XMEGA B [DATASHEET]
8291B–AVR–01/2013
7.10.5 RC32KCAL – 32kHz Oscillator Calibration register
 Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration byte
This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the signature
row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz. The register
can also be written from software to calibrate the oscillator frequency during normal operation.
7.10.6 PLLCTRL – PLL Control register
 Bit 7:6 – PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to Table 7-9.
Table 7-9. PLL clock source selection.
Notes: 1. The 32.768kHz TOSC cannot be selected as the source for the PLL. An external clock must be a minimum 0.4MHz to be used as the source clock.
 Bit 5 – PLLDIV: PLL Divided Output Enable
Setting this bit will divide the output from the PLL by 2.
 Bit 4:0 – PLLFAC[4:0]: Multiplication Factor
These bits select the multiplication factor for the PLL. The multiplication factor can be in the range of from 1x to 31x.
7.10.7 DFLLCTRL – DFLL Control register
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 76543210
+0x04 RC32KCAL[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value x x x x x x x x
Bit 76543210
+0x05 PLLSRC[1:0] PLLDIV PLLFAC[4:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PLLSRC[1:0] Group Configuration PLL Input Source
00 RC2M 2MHz internal oscillator
01 — Reserved
10 RC32M 32MHz internal oscillator
11 XOSC External clock source
(1)
Bit 765432 1 0
+0x06
– – – – – RC32MCREF[1:0] RC2MCREF
Read/Write R RRRRR/WR/WR/W
Initial Value 0 0 0000 0 0