Datasheet

89
XMEGA B [DATASHEET]
8291B–AVR–01/2013
7.10 Register Description – Oscillator
7.10.1 CTRL – Control register
 Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4 – PLLEN: PLL Enable
Setting this bit enables the PLL. Before the PLL is enabled, it must be configured with the desired multiplication factor
and clock source. See ”STATUS – Status register” on page 89..
 Bit 3 – XOSCEN: External Oscillator Enable
Setting this bit enables the selected external clock source. Refer to “XOSCCTRL – XOSC Control register” on page 90
for details on how to select the external clock source. The external clock source should be allowed time to stabilize
before it is selected as the source for the system clock. See ”STATUS – Status register” on page 89.
 Bit 2 – RC32KEN: 32.768kHz Internal Oscillator Enable
Setting this bit enables the 32.768kHz internal oscillator. The oscillator must be stable before it is selected as the source
for the system clock. See ”STATUS – Status register” on page 89.
 Bit 1 – RC32MEN: 32MHz Internal Oscillator Enable
Setting this bit will enable the 32MHz internal oscillator. The oscillator must be stable before it is selected as the source
for the system clock. See ”STATUS – Status register” on page 89.
 Bit 0 – RC2MEN: 2MHz Internal Oscillator Enable
Setting this bit enables the 2MHz internal oscillator. The oscillator must be stable before it is selected as the source for
the system clock. See ”STATUS – Status register” on page 89.
By default, the 2MHz internal oscillator is enabled and this bit is set.
7.10.2 STATUS – Status register
 Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4 – PLLRDY: PLL Ready
This flag is set when the PLL has locked on the selected frequency and is ready to be used as the system clock source.
 Bit 3 – XOSCRDY: External Clock Source Ready
This flag is set when the external clock source is stable and is ready to be used as the system clock source.
 Bit 2 – RC32KRDY: 32.768kHz Internal Oscillator Ready
This flag is set when the 32.768kHz internal oscillator is stable and is ready to be used as the system clock source.
 Bit 1 – RC32MRDY: 32MHz Internal Oscillator Ready
This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the system clock source.
Bit 76543210
+0x00
– – – PLLEN XOSCEN RC32KEN RC32MEN RC2MEN
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
+0x01
– – – PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0